xref: /llvm-project/llvm/test/CodeGen/PowerPC/aix-vec_extract_p9.ll (revision c2e7c9cb33acbd118fe5011a1607d6cf8e21de34) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-64
3; RUN: llc -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff -vec-extabi -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-32
4
5define zeroext i8 @test1(<16 x i8> %a, i32 signext %index) {
6; CHECK-64-LABEL: test1:
7; CHECK-64:       # %bb.0: # %entry
8; CHECK-64-NEXT:    clrldi 3, 3, 32
9; CHECK-64-NEXT:    vextublx 3, 3, 2
10; CHECK-64-NEXT:    clrldi 3, 3, 56
11; CHECK-64-NEXT:    blr
12;
13; CHECK-32-LABEL: test1:
14; CHECK-32:       # %bb.0: # %entry
15; CHECK-32-NEXT:    addi 4, 1, -16
16; CHECK-32-NEXT:    clrlwi 3, 3, 28
17; CHECK-32-NEXT:    stxv 34, -16(1)
18; CHECK-32-NEXT:    lbzx 3, 4, 3
19; CHECK-32-NEXT:    blr
20entry:
21  %vecext = extractelement <16 x i8> %a, i32 %index
22  ret i8 %vecext
23}
24
25define signext i8 @test2(<16 x i8> %a, i32 signext %index) {
26; CHECK-64-LABEL: test2:
27; CHECK-64:       # %bb.0: # %entry
28; CHECK-64-NEXT:    clrldi 3, 3, 32
29; CHECK-64-NEXT:    vextublx 3, 3, 2
30; CHECK-64-NEXT:    extsb 3, 3
31; CHECK-64-NEXT:    blr
32;
33; CHECK-32-LABEL: test2:
34; CHECK-32:       # %bb.0: # %entry
35; CHECK-32-NEXT:    addi 4, 1, -16
36; CHECK-32-NEXT:    clrlwi 3, 3, 28
37; CHECK-32-NEXT:    stxv 34, -16(1)
38; CHECK-32-NEXT:    lbzx 3, 4, 3
39; CHECK-32-NEXT:    extsb 3, 3
40; CHECK-32-NEXT:    blr
41entry:
42  %vecext = extractelement <16 x i8> %a, i32 %index
43  ret i8 %vecext
44}
45
46define zeroext i16 @test3(<8 x i16> %a, i32 signext %index) {
47; CHECK-64-LABEL: test3:
48; CHECK-64:       # %bb.0: # %entry
49; CHECK-64-NEXT:    clrldi 3, 3, 32
50; CHECK-64-NEXT:    rlwinm 3, 3, 1, 28, 30
51; CHECK-64-NEXT:    vextuhlx 3, 3, 2
52; CHECK-64-NEXT:    clrldi 3, 3, 48
53; CHECK-64-NEXT:    blr
54;
55; CHECK-32-LABEL: test3:
56; CHECK-32:       # %bb.0: # %entry
57; CHECK-32-NEXT:    addi 4, 1, -16
58; CHECK-32-NEXT:    rlwinm 3, 3, 1, 28, 30
59; CHECK-32-NEXT:    stxv 34, -16(1)
60; CHECK-32-NEXT:    lhzx 3, 4, 3
61; CHECK-32-NEXT:    blr
62entry:
63  %vecext = extractelement <8 x i16> %a, i32 %index
64  ret i16 %vecext
65}
66
67define signext i16 @test4(<8 x i16> %a, i32 signext %index) {
68; CHECK-64-LABEL: test4:
69; CHECK-64:       # %bb.0: # %entry
70; CHECK-64-NEXT:    clrldi 3, 3, 32
71; CHECK-64-NEXT:    rlwinm 3, 3, 1, 28, 30
72; CHECK-64-NEXT:    vextuhlx 3, 3, 2
73; CHECK-64-NEXT:    extsh 3, 3
74; CHECK-64-NEXT:    blr
75;
76; CHECK-32-LABEL: test4:
77; CHECK-32:       # %bb.0: # %entry
78; CHECK-32-NEXT:    addi 4, 1, -16
79; CHECK-32-NEXT:    rlwinm 3, 3, 1, 28, 30
80; CHECK-32-NEXT:    stxv 34, -16(1)
81; CHECK-32-NEXT:    lhax 3, 4, 3
82; CHECK-32-NEXT:    blr
83entry:
84  %vecext = extractelement <8 x i16> %a, i32 %index
85  ret i16 %vecext
86}
87
88define zeroext i32 @test5(<4 x i32> %a, i32 signext %index) {
89; CHECK-64-LABEL: test5:
90; CHECK-64:       # %bb.0: # %entry
91; CHECK-64-NEXT:    clrldi 3, 3, 32
92; CHECK-64-NEXT:    rlwinm 3, 3, 2, 28, 29
93; CHECK-64-NEXT:    vextuwlx 3, 3, 2
94; CHECK-64-NEXT:    blr
95;
96; CHECK-32-LABEL: test5:
97; CHECK-32:       # %bb.0: # %entry
98; CHECK-32-NEXT:    addi 4, 1, -16
99; CHECK-32-NEXT:    rlwinm 3, 3, 2, 28, 29
100; CHECK-32-NEXT:    stxv 34, -16(1)
101; CHECK-32-NEXT:    lwzx 3, 4, 3
102; CHECK-32-NEXT:    blr
103entry:
104  %vecext = extractelement <4 x i32> %a, i32 %index
105  ret i32 %vecext
106}
107
108define signext i32 @test6(<4 x i32> %a, i32 signext %index) {
109; CHECK-64-LABEL: test6:
110; CHECK-64:       # %bb.0: # %entry
111; CHECK-64-NEXT:    clrldi 3, 3, 32
112; CHECK-64-NEXT:    rlwinm 3, 3, 2, 28, 29
113; CHECK-64-NEXT:    vextuwlx 3, 3, 2
114; CHECK-64-NEXT:    extsw 3, 3
115; CHECK-64-NEXT:    blr
116;
117; CHECK-32-LABEL: test6:
118; CHECK-32:       # %bb.0: # %entry
119; CHECK-32-NEXT:    addi 4, 1, -16
120; CHECK-32-NEXT:    rlwinm 3, 3, 2, 28, 29
121; CHECK-32-NEXT:    stxv 34, -16(1)
122; CHECK-32-NEXT:    lwzx 3, 4, 3
123; CHECK-32-NEXT:    blr
124entry:
125  %vecext = extractelement <4 x i32> %a, i32 %index
126  ret i32 %vecext
127}
128
129; Test with immediate index
130define zeroext i8 @test7(<16 x i8> %a) {
131; CHECK-64-LABEL: test7:
132; CHECK-64:       # %bb.0: # %entry
133; CHECK-64-NEXT:    li 3, 1
134; CHECK-64-NEXT:    vextublx 3, 3, 2
135; CHECK-64-NEXT:    clrldi 3, 3, 56
136; CHECK-64-NEXT:    blr
137;
138; CHECK-32-LABEL: test7:
139; CHECK-32:       # %bb.0: # %entry
140; CHECK-32-NEXT:    stxv 34, -16(1)
141; CHECK-32-NEXT:    lbz 3, -15(1)
142; CHECK-32-NEXT:    blr
143entry:
144  %vecext = extractelement <16 x i8> %a, i32 1
145  ret i8 %vecext
146}
147
148define zeroext i16 @test8(<8 x i16> %a) {
149; CHECK-64-LABEL: test8:
150; CHECK-64:       # %bb.0: # %entry
151; CHECK-64-NEXT:    li 3, 2
152; CHECK-64-NEXT:    vextuhlx 3, 3, 2
153; CHECK-64-NEXT:    clrldi 3, 3, 48
154; CHECK-64-NEXT:    blr
155;
156; CHECK-32-LABEL: test8:
157; CHECK-32:       # %bb.0: # %entry
158; CHECK-32-NEXT:    stxv 34, -16(1)
159; CHECK-32-NEXT:    lhz 3, -14(1)
160; CHECK-32-NEXT:    blr
161entry:
162  %vecext = extractelement <8 x i16> %a, i32 1
163  ret i16 %vecext
164}
165
166define zeroext i32 @test9(<4 x i32> %a) {
167; CHECK-64-LABEL: test9:
168; CHECK-64:       # %bb.0:
169; CHECK-64-NEXT:    li 3, 12
170; CHECK-64-NEXT:    vextuwlx 3, 3, 2
171; CHECK-64-NEXT:    blr
172;
173; CHECK-32-LABEL: test9:
174; CHECK-32:       # %bb.0:
175; CHECK-32-NEXT:    stxv 34, -16(1)
176; CHECK-32-NEXT:    lwz 3, -4(1)
177; CHECK-32-NEXT:    blr
178  %vecext = extractelement <4 x i32> %a, i32 3
179  ret i32 %vecext
180}
181