1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 2; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec \ 3; RUN: -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s \ 4; RUN: --check-prefix=SMALL32 5; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec \ 6; RUN: -mtriple powerpc-ibm-aix-xcoff --code-model=large < %s \ 7; RUN: | FileCheck %s --check-prefix=LARGE32 8; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec \ 9; RUN: -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s \ 10; RUN: --check-prefix=SMALL64 11; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec \ 12; RUN: -mtriple powerpc64-ibm-aix-xcoff --code-model=large < %s \ 13; RUN: | FileCheck %s --check-prefix=LARGE64 14 15@TGInit = thread_local global i64 1, align 8 16@TWInit = weak thread_local global i64 1, align 8 17@GInit = global i64 1, align 8 18@TIUninit = internal thread_local global i64 0, align 8 19@TIInit = internal thread_local global i64 1, align 8 20 21; Function Attrs: nofree norecurse nounwind willreturn writeonly 22define void @storesTGInit(i64 %Val) #0 { 23; SMALL32-LABEL: storesTGInit: 24; SMALL32: # %bb.0: # %entry 25; SMALL32-NEXT: mflr 0 26; SMALL32-NEXT: stwu 1, -32(1) 27; SMALL32-NEXT: mr 6, 4 28; SMALL32-NEXT: mr 7, 3 29; SMALL32-NEXT: lwz 3, L..C0(2) # target-flags(ppc-tlsgdm) @TGInit 30; SMALL32-NEXT: lwz 4, L..C1(2) # target-flags(ppc-tlsgd) @TGInit 31; SMALL32-NEXT: stw 0, 40(1) 32; SMALL32-NEXT: bla .__tls_get_addr[PR] 33; SMALL32-NEXT: stw 6, 4(3) 34; SMALL32-NEXT: stw 7, 0(3) 35; SMALL32-NEXT: addi 1, 1, 32 36; SMALL32-NEXT: lwz 0, 8(1) 37; SMALL32-NEXT: mtlr 0 38; SMALL32-NEXT: blr 39; 40; LARGE32-LABEL: storesTGInit: 41; LARGE32: # %bb.0: # %entry 42; LARGE32-NEXT: mflr 0 43; LARGE32-NEXT: stwu 1, -32(1) 44; LARGE32-NEXT: stw 0, 40(1) 45; LARGE32-NEXT: mr 6, 4 46; LARGE32-NEXT: mr 7, 3 47; LARGE32-NEXT: addis 3, L..C0@u(2) 48; LARGE32-NEXT: addis 4, L..C1@u(2) 49; LARGE32-NEXT: lwz 3, L..C0@l(3) 50; LARGE32-NEXT: lwz 4, L..C1@l(4) 51; LARGE32-NEXT: bla .__tls_get_addr[PR] 52; LARGE32-NEXT: stw 6, 4(3) 53; LARGE32-NEXT: stw 7, 0(3) 54; LARGE32-NEXT: addi 1, 1, 32 55; LARGE32-NEXT: lwz 0, 8(1) 56; LARGE32-NEXT: mtlr 0 57; LARGE32-NEXT: blr 58; 59; SMALL64-LABEL: storesTGInit: 60; SMALL64: # %bb.0: # %entry 61; SMALL64-NEXT: mflr 0 62; SMALL64-NEXT: stdu 1, -48(1) 63; SMALL64-NEXT: mr 6, 3 64; SMALL64-NEXT: ld 3, L..C0(2) # target-flags(ppc-tlsgdm) @TGInit 65; SMALL64-NEXT: ld 4, L..C1(2) # target-flags(ppc-tlsgd) @TGInit 66; SMALL64-NEXT: std 0, 64(1) 67; SMALL64-NEXT: bla .__tls_get_addr[PR] 68; SMALL64-NEXT: std 6, 0(3) 69; SMALL64-NEXT: addi 1, 1, 48 70; SMALL64-NEXT: ld 0, 16(1) 71; SMALL64-NEXT: mtlr 0 72; SMALL64-NEXT: blr 73; 74; LARGE64-LABEL: storesTGInit: 75; LARGE64: # %bb.0: # %entry 76; LARGE64-NEXT: mflr 0 77; LARGE64-NEXT: stdu 1, -48(1) 78; LARGE64-NEXT: mr 6, 3 79; LARGE64-NEXT: addis 3, L..C0@u(2) 80; LARGE64-NEXT: addis 4, L..C1@u(2) 81; LARGE64-NEXT: std 0, 64(1) 82; LARGE64-NEXT: ld 3, L..C0@l(3) 83; LARGE64-NEXT: ld 4, L..C1@l(4) 84; LARGE64-NEXT: bla .__tls_get_addr[PR] 85; LARGE64-NEXT: std 6, 0(3) 86; LARGE64-NEXT: addi 1, 1, 48 87; LARGE64-NEXT: ld 0, 16(1) 88; LARGE64-NEXT: mtlr 0 89; LARGE64-NEXT: blr 90entry: 91 store i64 %Val, ptr @TGInit, align 8 92 ret void 93} 94 95; Function Attrs: nofree norecurse nounwind willreturn writeonly 96define void @storesTIUninit(i64 %Val) #0 { 97; SMALL32-LABEL: storesTIUninit: 98; SMALL32: # %bb.0: # %entry 99; SMALL32-NEXT: mflr 0 100; SMALL32-NEXT: stwu 1, -32(1) 101; SMALL32-NEXT: mr 7, 3 102; SMALL32-NEXT: lwz 3, L..C2(2) # target-flags(ppc-tlsldm) @"_$TLSML" 103; SMALL32-NEXT: stw 0, 40(1) 104; SMALL32-NEXT: mr 6, 4 105; SMALL32-NEXT: bla .__tls_get_mod[PR] 106; SMALL32-NEXT: lwz 4, L..C3(2) # target-flags(ppc-tlsld) @TIUninit 107; SMALL32-NEXT: stwux 7, 3, 4 108; SMALL32-NEXT: stw 6, 4(3) 109; SMALL32-NEXT: addi 1, 1, 32 110; SMALL32-NEXT: lwz 0, 8(1) 111; SMALL32-NEXT: mtlr 0 112; SMALL32-NEXT: blr 113; 114; LARGE32-LABEL: storesTIUninit: 115; LARGE32: # %bb.0: # %entry 116; LARGE32-NEXT: mflr 0 117; LARGE32-NEXT: stwu 1, -32(1) 118; LARGE32-NEXT: stw 0, 40(1) 119; LARGE32-NEXT: mr 7, 3 120; LARGE32-NEXT: addis 8, L..C2@u(2) 121; LARGE32-NEXT: addis 3, L..C3@u(2) 122; LARGE32-NEXT: mr 6, 4 123; LARGE32-NEXT: lwz 3, L..C3@l(3) 124; LARGE32-NEXT: bla .__tls_get_mod[PR] 125; LARGE32-NEXT: lwz 4, L..C2@l(8) 126; LARGE32-NEXT: stwux 7, 3, 4 127; LARGE32-NEXT: stw 6, 4(3) 128; LARGE32-NEXT: addi 1, 1, 32 129; LARGE32-NEXT: lwz 0, 8(1) 130; LARGE32-NEXT: mtlr 0 131; LARGE32-NEXT: blr 132; 133; SMALL64-LABEL: storesTIUninit: 134; SMALL64: # %bb.0: # %entry 135; SMALL64-NEXT: mflr 0 136; SMALL64-NEXT: stdu 1, -48(1) 137; SMALL64-NEXT: mr 6, 3 138; SMALL64-NEXT: ld 3, L..C2(2) # target-flags(ppc-tlsldm) @"_$TLSML" 139; SMALL64-NEXT: std 0, 64(1) 140; SMALL64-NEXT: bla .__tls_get_mod[PR] 141; SMALL64-NEXT: ld 4, L..C3(2) # target-flags(ppc-tlsld) @TIUninit 142; SMALL64-NEXT: stdx 6, 3, 4 143; SMALL64-NEXT: addi 1, 1, 48 144; SMALL64-NEXT: ld 0, 16(1) 145; SMALL64-NEXT: mtlr 0 146; SMALL64-NEXT: blr 147; 148; LARGE64-LABEL: storesTIUninit: 149; LARGE64: # %bb.0: # %entry 150; LARGE64-NEXT: mflr 0 151; LARGE64-NEXT: stdu 1, -48(1) 152; LARGE64-NEXT: mr 6, 3 153; LARGE64-NEXT: addis 3, L..C2@u(2) 154; LARGE64-NEXT: std 0, 64(1) 155; LARGE64-NEXT: addis 7, L..C3@u(2) 156; LARGE64-NEXT: ld 3, L..C2@l(3) 157; LARGE64-NEXT: bla .__tls_get_mod[PR] 158; LARGE64-NEXT: ld 4, L..C3@l(7) 159; LARGE64-NEXT: stdx 6, 3, 4 160; LARGE64-NEXT: addi 1, 1, 48 161; LARGE64-NEXT: ld 0, 16(1) 162; LARGE64-NEXT: mtlr 0 163; LARGE64-NEXT: blr 164entry: 165 store i64 %Val, ptr @TIUninit, align 8 166 ret void 167} 168 169; Function Attrs: nofree norecurse nounwind willreturn writeonly 170define void @storesTIInit(i64 %Val) #0 { 171; SMALL32-LABEL: storesTIInit: 172; SMALL32: # %bb.0: # %entry 173; SMALL32-NEXT: mflr 0 174; SMALL32-NEXT: stwu 1, -32(1) 175; SMALL32-NEXT: mr 7, 3 176; SMALL32-NEXT: lwz 3, L..C2(2) # target-flags(ppc-tlsldm) @"_$TLSML" 177; SMALL32-NEXT: stw 0, 40(1) 178; SMALL32-NEXT: mr 6, 4 179; SMALL32-NEXT: bla .__tls_get_mod[PR] 180; SMALL32-NEXT: lwz 4, L..C4(2) # target-flags(ppc-tlsld) @TIInit 181; SMALL32-NEXT: stwux 7, 3, 4 182; SMALL32-NEXT: stw 6, 4(3) 183; SMALL32-NEXT: addi 1, 1, 32 184; SMALL32-NEXT: lwz 0, 8(1) 185; SMALL32-NEXT: mtlr 0 186; SMALL32-NEXT: blr 187; 188; LARGE32-LABEL: storesTIInit: 189; LARGE32: # %bb.0: # %entry 190; LARGE32-NEXT: mflr 0 191; LARGE32-NEXT: stwu 1, -32(1) 192; LARGE32-NEXT: stw 0, 40(1) 193; LARGE32-NEXT: mr 7, 3 194; LARGE32-NEXT: addis 8, L..C4@u(2) 195; LARGE32-NEXT: addis 3, L..C3@u(2) 196; LARGE32-NEXT: mr 6, 4 197; LARGE32-NEXT: lwz 3, L..C3@l(3) 198; LARGE32-NEXT: bla .__tls_get_mod[PR] 199; LARGE32-NEXT: lwz 4, L..C4@l(8) 200; LARGE32-NEXT: stwux 7, 3, 4 201; LARGE32-NEXT: stw 6, 4(3) 202; LARGE32-NEXT: addi 1, 1, 32 203; LARGE32-NEXT: lwz 0, 8(1) 204; LARGE32-NEXT: mtlr 0 205; LARGE32-NEXT: blr 206; 207; SMALL64-LABEL: storesTIInit: 208; SMALL64: # %bb.0: # %entry 209; SMALL64-NEXT: mflr 0 210; SMALL64-NEXT: stdu 1, -48(1) 211; SMALL64-NEXT: mr 6, 3 212; SMALL64-NEXT: ld 3, L..C2(2) # target-flags(ppc-tlsldm) @"_$TLSML" 213; SMALL64-NEXT: std 0, 64(1) 214; SMALL64-NEXT: bla .__tls_get_mod[PR] 215; SMALL64-NEXT: ld 4, L..C4(2) # target-flags(ppc-tlsld) @TIInit 216; SMALL64-NEXT: stdx 6, 3, 4 217; SMALL64-NEXT: addi 1, 1, 48 218; SMALL64-NEXT: ld 0, 16(1) 219; SMALL64-NEXT: mtlr 0 220; SMALL64-NEXT: blr 221; 222; LARGE64-LABEL: storesTIInit: 223; LARGE64: # %bb.0: # %entry 224; LARGE64-NEXT: mflr 0 225; LARGE64-NEXT: stdu 1, -48(1) 226; LARGE64-NEXT: mr 6, 3 227; LARGE64-NEXT: addis 3, L..C2@u(2) 228; LARGE64-NEXT: std 0, 64(1) 229; LARGE64-NEXT: addis 7, L..C4@u(2) 230; LARGE64-NEXT: ld 3, L..C2@l(3) 231; LARGE64-NEXT: bla .__tls_get_mod[PR] 232; LARGE64-NEXT: ld 4, L..C4@l(7) 233; LARGE64-NEXT: stdx 6, 3, 4 234; LARGE64-NEXT: addi 1, 1, 48 235; LARGE64-NEXT: ld 0, 16(1) 236; LARGE64-NEXT: mtlr 0 237; LARGE64-NEXT: blr 238entry: 239 store i64 %Val, ptr @TIInit, align 8 240 ret void 241} 242 243; Function Attrs: nofree norecurse nounwind willreturn writeonly 244define void @storesTWInit(i64 %Val) #0 { 245; SMALL32-LABEL: storesTWInit: 246; SMALL32: # %bb.0: # %entry 247; SMALL32-NEXT: mflr 0 248; SMALL32-NEXT: stwu 1, -32(1) 249; SMALL32-NEXT: mr 6, 4 250; SMALL32-NEXT: mr 7, 3 251; SMALL32-NEXT: lwz 3, L..C5(2) # target-flags(ppc-tlsgdm) @TWInit 252; SMALL32-NEXT: lwz 4, L..C6(2) # target-flags(ppc-tlsgd) @TWInit 253; SMALL32-NEXT: stw 0, 40(1) 254; SMALL32-NEXT: bla .__tls_get_addr[PR] 255; SMALL32-NEXT: stw 6, 4(3) 256; SMALL32-NEXT: stw 7, 0(3) 257; SMALL32-NEXT: addi 1, 1, 32 258; SMALL32-NEXT: lwz 0, 8(1) 259; SMALL32-NEXT: mtlr 0 260; SMALL32-NEXT: blr 261; 262; LARGE32-LABEL: storesTWInit: 263; LARGE32: # %bb.0: # %entry 264; LARGE32-NEXT: mflr 0 265; LARGE32-NEXT: stwu 1, -32(1) 266; LARGE32-NEXT: stw 0, 40(1) 267; LARGE32-NEXT: mr 6, 4 268; LARGE32-NEXT: mr 7, 3 269; LARGE32-NEXT: addis 3, L..C5@u(2) 270; LARGE32-NEXT: addis 4, L..C6@u(2) 271; LARGE32-NEXT: lwz 3, L..C5@l(3) 272; LARGE32-NEXT: lwz 4, L..C6@l(4) 273; LARGE32-NEXT: bla .__tls_get_addr[PR] 274; LARGE32-NEXT: stw 6, 4(3) 275; LARGE32-NEXT: stw 7, 0(3) 276; LARGE32-NEXT: addi 1, 1, 32 277; LARGE32-NEXT: lwz 0, 8(1) 278; LARGE32-NEXT: mtlr 0 279; LARGE32-NEXT: blr 280; 281; SMALL64-LABEL: storesTWInit: 282; SMALL64: # %bb.0: # %entry 283; SMALL64-NEXT: mflr 0 284; SMALL64-NEXT: stdu 1, -48(1) 285; SMALL64-NEXT: mr 6, 3 286; SMALL64-NEXT: ld 3, L..C5(2) # target-flags(ppc-tlsgdm) @TWInit 287; SMALL64-NEXT: ld 4, L..C6(2) # target-flags(ppc-tlsgd) @TWInit 288; SMALL64-NEXT: std 0, 64(1) 289; SMALL64-NEXT: bla .__tls_get_addr[PR] 290; SMALL64-NEXT: std 6, 0(3) 291; SMALL64-NEXT: addi 1, 1, 48 292; SMALL64-NEXT: ld 0, 16(1) 293; SMALL64-NEXT: mtlr 0 294; SMALL64-NEXT: blr 295; 296; LARGE64-LABEL: storesTWInit: 297; LARGE64: # %bb.0: # %entry 298; LARGE64-NEXT: mflr 0 299; LARGE64-NEXT: stdu 1, -48(1) 300; LARGE64-NEXT: mr 6, 3 301; LARGE64-NEXT: addis 3, L..C5@u(2) 302; LARGE64-NEXT: addis 4, L..C6@u(2) 303; LARGE64-NEXT: std 0, 64(1) 304; LARGE64-NEXT: ld 3, L..C5@l(3) 305; LARGE64-NEXT: ld 4, L..C6@l(4) 306; LARGE64-NEXT: bla .__tls_get_addr[PR] 307; LARGE64-NEXT: std 6, 0(3) 308; LARGE64-NEXT: addi 1, 1, 48 309; LARGE64-NEXT: ld 0, 16(1) 310; LARGE64-NEXT: mtlr 0 311; LARGE64-NEXT: blr 312entry: 313 store i64 %Val, ptr @TWInit, align 8 314 ret void 315} 316 317; Function Attrs: norecurse nounwind readonly willreturn 318define i64 @loadsTGInit() #1 { 319; SMALL32-LABEL: loadsTGInit: 320; SMALL32: # %bb.0: # %entry 321; SMALL32-NEXT: mflr 0 322; SMALL32-NEXT: stwu 1, -32(1) 323; SMALL32-NEXT: lwz 3, L..C0(2) # target-flags(ppc-tlsgdm) @TGInit 324; SMALL32-NEXT: lwz 4, L..C1(2) # target-flags(ppc-tlsgd) @TGInit 325; SMALL32-NEXT: stw 0, 40(1) 326; SMALL32-NEXT: bla .__tls_get_addr[PR] 327; SMALL32-NEXT: lwz 4, L..C7(2) # @GInit 328; SMALL32-NEXT: lwz 5, 4(3) 329; SMALL32-NEXT: lwz 6, 4(4) 330; SMALL32-NEXT: lwz 3, 0(3) 331; SMALL32-NEXT: lwz 7, 0(4) 332; SMALL32-NEXT: addc 4, 6, 5 333; SMALL32-NEXT: adde 3, 7, 3 334; SMALL32-NEXT: addi 1, 1, 32 335; SMALL32-NEXT: lwz 0, 8(1) 336; SMALL32-NEXT: mtlr 0 337; SMALL32-NEXT: blr 338; 339; LARGE32-LABEL: loadsTGInit: 340; LARGE32: # %bb.0: # %entry 341; LARGE32-NEXT: mflr 0 342; LARGE32-NEXT: stwu 1, -32(1) 343; LARGE32-NEXT: stw 0, 40(1) 344; LARGE32-NEXT: addis 3, L..C0@u(2) 345; LARGE32-NEXT: addis 4, L..C1@u(2) 346; LARGE32-NEXT: lwz 3, L..C0@l(3) 347; LARGE32-NEXT: lwz 4, L..C1@l(4) 348; LARGE32-NEXT: bla .__tls_get_addr[PR] 349; LARGE32-NEXT: lwz 4, 4(3) 350; LARGE32-NEXT: lwz 3, 0(3) 351; LARGE32-NEXT: addis 5, L..C7@u(2) 352; LARGE32-NEXT: lwz 5, L..C7@l(5) 353; LARGE32-NEXT: lwz 6, 4(5) 354; LARGE32-NEXT: lwz 5, 0(5) 355; LARGE32-NEXT: addc 4, 6, 4 356; LARGE32-NEXT: adde 3, 5, 3 357; LARGE32-NEXT: addi 1, 1, 32 358; LARGE32-NEXT: lwz 0, 8(1) 359; LARGE32-NEXT: mtlr 0 360; LARGE32-NEXT: blr 361; 362; SMALL64-LABEL: loadsTGInit: 363; SMALL64: # %bb.0: # %entry 364; SMALL64-NEXT: mflr 0 365; SMALL64-NEXT: stdu 1, -48(1) 366; SMALL64-NEXT: ld 3, L..C0(2) # target-flags(ppc-tlsgdm) @TGInit 367; SMALL64-NEXT: ld 4, L..C1(2) # target-flags(ppc-tlsgd) @TGInit 368; SMALL64-NEXT: std 0, 64(1) 369; SMALL64-NEXT: bla .__tls_get_addr[PR] 370; SMALL64-NEXT: ld 4, L..C7(2) # @GInit 371; SMALL64-NEXT: ld 3, 0(3) 372; SMALL64-NEXT: ld 4, 0(4) 373; SMALL64-NEXT: add 3, 4, 3 374; SMALL64-NEXT: addi 1, 1, 48 375; SMALL64-NEXT: ld 0, 16(1) 376; SMALL64-NEXT: mtlr 0 377; SMALL64-NEXT: blr 378; 379; LARGE64-LABEL: loadsTGInit: 380; LARGE64: # %bb.0: # %entry 381; LARGE64-NEXT: mflr 0 382; LARGE64-NEXT: stdu 1, -48(1) 383; LARGE64-NEXT: addis 3, L..C0@u(2) 384; LARGE64-NEXT: addis 4, L..C1@u(2) 385; LARGE64-NEXT: std 0, 64(1) 386; LARGE64-NEXT: ld 3, L..C0@l(3) 387; LARGE64-NEXT: ld 4, L..C1@l(4) 388; LARGE64-NEXT: bla .__tls_get_addr[PR] 389; LARGE64-NEXT: addis 4, L..C7@u(2) 390; LARGE64-NEXT: ld 3, 0(3) 391; LARGE64-NEXT: ld 4, L..C7@l(4) 392; LARGE64-NEXT: ld 4, 0(4) 393; LARGE64-NEXT: add 3, 4, 3 394; LARGE64-NEXT: addi 1, 1, 48 395; LARGE64-NEXT: ld 0, 16(1) 396; LARGE64-NEXT: mtlr 0 397; LARGE64-NEXT: blr 398entry: 399 %0 = load i64, ptr @TGInit, align 8 400 %1 = load i64, ptr @GInit, align 8 401 %add = add nsw i64 %1, %0 402 ret i64 %add 403} 404 405; Function Attrs: norecurse nounwind readonly willreturn 406define i64 @loadsTIUninit() #1 { 407; SMALL32-LABEL: loadsTIUninit: 408; SMALL32: # %bb.0: # %entry 409; SMALL32-NEXT: mflr 0 410; SMALL32-NEXT: stwu 1, -32(1) 411; SMALL32-NEXT: lwz 3, L..C2(2) # target-flags(ppc-tlsldm) @"_$TLSML" 412; SMALL32-NEXT: stw 0, 40(1) 413; SMALL32-NEXT: bla .__tls_get_mod[PR] 414; SMALL32-NEXT: lwz 4, L..C3(2) # target-flags(ppc-tlsld) @TIUninit 415; SMALL32-NEXT: lwz 5, L..C7(2) # @GInit 416; SMALL32-NEXT: lwzux 6, 3, 4 417; SMALL32-NEXT: lwz 4, 4(5) 418; SMALL32-NEXT: lwz 3, 4(3) 419; SMALL32-NEXT: lwz 5, 0(5) 420; SMALL32-NEXT: addc 4, 4, 3 421; SMALL32-NEXT: adde 3, 5, 6 422; SMALL32-NEXT: addi 1, 1, 32 423; SMALL32-NEXT: lwz 0, 8(1) 424; SMALL32-NEXT: mtlr 0 425; SMALL32-NEXT: blr 426; 427; LARGE32-LABEL: loadsTIUninit: 428; LARGE32: # %bb.0: # %entry 429; LARGE32-NEXT: mflr 0 430; LARGE32-NEXT: stwu 1, -32(1) 431; LARGE32-NEXT: stw 0, 40(1) 432; LARGE32-NEXT: addis 6, L..C2@u(2) 433; LARGE32-NEXT: addis 3, L..C3@u(2) 434; LARGE32-NEXT: lwz 3, L..C3@l(3) 435; LARGE32-NEXT: bla .__tls_get_mod[PR] 436; LARGE32-NEXT: lwz 4, L..C2@l(6) 437; LARGE32-NEXT: lwzux 5, 3, 4 438; LARGE32-NEXT: lwz 3, 4(3) 439; LARGE32-NEXT: addis 4, L..C7@u(2) 440; LARGE32-NEXT: lwz 4, L..C7@l(4) 441; LARGE32-NEXT: lwz 6, 4(4) 442; LARGE32-NEXT: lwz 7, 0(4) 443; LARGE32-NEXT: addc 4, 6, 3 444; LARGE32-NEXT: adde 3, 7, 5 445; LARGE32-NEXT: addi 1, 1, 32 446; LARGE32-NEXT: lwz 0, 8(1) 447; LARGE32-NEXT: mtlr 0 448; LARGE32-NEXT: blr 449; 450; SMALL64-LABEL: loadsTIUninit: 451; SMALL64: # %bb.0: # %entry 452; SMALL64-NEXT: mflr 0 453; SMALL64-NEXT: stdu 1, -48(1) 454; SMALL64-NEXT: ld 3, L..C2(2) # target-flags(ppc-tlsldm) @"_$TLSML" 455; SMALL64-NEXT: std 0, 64(1) 456; SMALL64-NEXT: bla .__tls_get_mod[PR] 457; SMALL64-NEXT: ld 4, L..C3(2) # target-flags(ppc-tlsld) @TIUninit 458; SMALL64-NEXT: ldx 3, 3, 4 459; SMALL64-NEXT: ld 4, L..C7(2) # @GInit 460; SMALL64-NEXT: ld 4, 0(4) 461; SMALL64-NEXT: add 3, 4, 3 462; SMALL64-NEXT: addi 1, 1, 48 463; SMALL64-NEXT: ld 0, 16(1) 464; SMALL64-NEXT: mtlr 0 465; SMALL64-NEXT: blr 466; 467; LARGE64-LABEL: loadsTIUninit: 468; LARGE64: # %bb.0: # %entry 469; LARGE64-NEXT: mflr 0 470; LARGE64-NEXT: stdu 1, -48(1) 471; LARGE64-NEXT: addis 3, L..C2@u(2) 472; LARGE64-NEXT: std 0, 64(1) 473; LARGE64-NEXT: addis 6, L..C3@u(2) 474; LARGE64-NEXT: ld 3, L..C2@l(3) 475; LARGE64-NEXT: bla .__tls_get_mod[PR] 476; LARGE64-NEXT: ld 4, L..C3@l(6) 477; LARGE64-NEXT: addis 5, L..C7@u(2) 478; LARGE64-NEXT: ldx 3, 3, 4 479; LARGE64-NEXT: ld 4, L..C7@l(5) 480; LARGE64-NEXT: ld 4, 0(4) 481; LARGE64-NEXT: add 3, 4, 3 482; LARGE64-NEXT: addi 1, 1, 48 483; LARGE64-NEXT: ld 0, 16(1) 484; LARGE64-NEXT: mtlr 0 485; LARGE64-NEXT: blr 486entry: 487 %0 = load i64, ptr @TIUninit, align 8 488 %1 = load i64, ptr @GInit, align 8 489 %add = add nsw i64 %1, %0 490 ret i64 %add 491} 492 493; Function Attrs: norecurse nounwind readonly willreturn 494define i64 @loadsTIInit() #1 { 495; SMALL32-LABEL: loadsTIInit: 496; SMALL32: # %bb.0: # %entry 497; SMALL32-NEXT: mflr 0 498; SMALL32-NEXT: stwu 1, -32(1) 499; SMALL32-NEXT: lwz 3, L..C2(2) # target-flags(ppc-tlsldm) @"_$TLSML" 500; SMALL32-NEXT: stw 0, 40(1) 501; SMALL32-NEXT: bla .__tls_get_mod[PR] 502; SMALL32-NEXT: lwz 4, L..C4(2) # target-flags(ppc-tlsld) @TIInit 503; SMALL32-NEXT: lwz 5, L..C7(2) # @GInit 504; SMALL32-NEXT: lwzux 6, 3, 4 505; SMALL32-NEXT: lwz 4, 4(5) 506; SMALL32-NEXT: lwz 3, 4(3) 507; SMALL32-NEXT: lwz 5, 0(5) 508; SMALL32-NEXT: addc 4, 4, 3 509; SMALL32-NEXT: adde 3, 5, 6 510; SMALL32-NEXT: addi 1, 1, 32 511; SMALL32-NEXT: lwz 0, 8(1) 512; SMALL32-NEXT: mtlr 0 513; SMALL32-NEXT: blr 514; 515; LARGE32-LABEL: loadsTIInit: 516; LARGE32: # %bb.0: # %entry 517; LARGE32-NEXT: mflr 0 518; LARGE32-NEXT: stwu 1, -32(1) 519; LARGE32-NEXT: stw 0, 40(1) 520; LARGE32-NEXT: addis 6, L..C4@u(2) 521; LARGE32-NEXT: addis 3, L..C3@u(2) 522; LARGE32-NEXT: lwz 3, L..C3@l(3) 523; LARGE32-NEXT: bla .__tls_get_mod[PR] 524; LARGE32-NEXT: lwz 4, L..C4@l(6) 525; LARGE32-NEXT: lwzux 5, 3, 4 526; LARGE32-NEXT: lwz 3, 4(3) 527; LARGE32-NEXT: addis 4, L..C7@u(2) 528; LARGE32-NEXT: lwz 4, L..C7@l(4) 529; LARGE32-NEXT: lwz 6, 4(4) 530; LARGE32-NEXT: lwz 7, 0(4) 531; LARGE32-NEXT: addc 4, 6, 3 532; LARGE32-NEXT: adde 3, 7, 5 533; LARGE32-NEXT: addi 1, 1, 32 534; LARGE32-NEXT: lwz 0, 8(1) 535; LARGE32-NEXT: mtlr 0 536; LARGE32-NEXT: blr 537; 538; SMALL64-LABEL: loadsTIInit: 539; SMALL64: # %bb.0: # %entry 540; SMALL64-NEXT: mflr 0 541; SMALL64-NEXT: stdu 1, -48(1) 542; SMALL64-NEXT: ld 3, L..C2(2) # target-flags(ppc-tlsldm) @"_$TLSML" 543; SMALL64-NEXT: std 0, 64(1) 544; SMALL64-NEXT: bla .__tls_get_mod[PR] 545; SMALL64-NEXT: ld 4, L..C4(2) # target-flags(ppc-tlsld) @TIInit 546; SMALL64-NEXT: ldx 3, 3, 4 547; SMALL64-NEXT: ld 4, L..C7(2) # @GInit 548; SMALL64-NEXT: ld 4, 0(4) 549; SMALL64-NEXT: add 3, 4, 3 550; SMALL64-NEXT: addi 1, 1, 48 551; SMALL64-NEXT: ld 0, 16(1) 552; SMALL64-NEXT: mtlr 0 553; SMALL64-NEXT: blr 554; 555; LARGE64-LABEL: loadsTIInit: 556; LARGE64: # %bb.0: # %entry 557; LARGE64-NEXT: mflr 0 558; LARGE64-NEXT: stdu 1, -48(1) 559; LARGE64-NEXT: addis 3, L..C2@u(2) 560; LARGE64-NEXT: std 0, 64(1) 561; LARGE64-NEXT: addis 6, L..C4@u(2) 562; LARGE64-NEXT: ld 3, L..C2@l(3) 563; LARGE64-NEXT: bla .__tls_get_mod[PR] 564; LARGE64-NEXT: ld 4, L..C4@l(6) 565; LARGE64-NEXT: addis 5, L..C7@u(2) 566; LARGE64-NEXT: ldx 3, 3, 4 567; LARGE64-NEXT: ld 4, L..C7@l(5) 568; LARGE64-NEXT: ld 4, 0(4) 569; LARGE64-NEXT: add 3, 4, 3 570; LARGE64-NEXT: addi 1, 1, 48 571; LARGE64-NEXT: ld 0, 16(1) 572; LARGE64-NEXT: mtlr 0 573; LARGE64-NEXT: blr 574entry: 575 %0 = load i64, ptr @TIInit, align 8 576 %1 = load i64, ptr @GInit, align 8 577 %add = add nsw i64 %1, %0 578 ret i64 %add 579} 580 581; Function Attrs: norecurse nounwind readonly willreturn 582define i64 @loadsTWInit() #1 { 583; SMALL32-LABEL: loadsTWInit: 584; SMALL32: # %bb.0: # %entry 585; SMALL32-NEXT: mflr 0 586; SMALL32-NEXT: stwu 1, -32(1) 587; SMALL32-NEXT: lwz 3, L..C5(2) # target-flags(ppc-tlsgdm) @TWInit 588; SMALL32-NEXT: lwz 4, L..C6(2) # target-flags(ppc-tlsgd) @TWInit 589; SMALL32-NEXT: stw 0, 40(1) 590; SMALL32-NEXT: bla .__tls_get_addr[PR] 591; SMALL32-NEXT: lwz 4, L..C7(2) # @GInit 592; SMALL32-NEXT: lwz 5, 4(3) 593; SMALL32-NEXT: lwz 6, 4(4) 594; SMALL32-NEXT: lwz 3, 0(3) 595; SMALL32-NEXT: lwz 7, 0(4) 596; SMALL32-NEXT: addc 4, 6, 5 597; SMALL32-NEXT: adde 3, 7, 3 598; SMALL32-NEXT: addi 1, 1, 32 599; SMALL32-NEXT: lwz 0, 8(1) 600; SMALL32-NEXT: mtlr 0 601; SMALL32-NEXT: blr 602; 603; LARGE32-LABEL: loadsTWInit: 604; LARGE32: # %bb.0: # %entry 605; LARGE32-NEXT: mflr 0 606; LARGE32-NEXT: stwu 1, -32(1) 607; LARGE32-NEXT: stw 0, 40(1) 608; LARGE32-NEXT: addis 3, L..C5@u(2) 609; LARGE32-NEXT: addis 4, L..C6@u(2) 610; LARGE32-NEXT: lwz 3, L..C5@l(3) 611; LARGE32-NEXT: lwz 4, L..C6@l(4) 612; LARGE32-NEXT: bla .__tls_get_addr[PR] 613; LARGE32-NEXT: lwz 4, 4(3) 614; LARGE32-NEXT: lwz 3, 0(3) 615; LARGE32-NEXT: addis 5, L..C7@u(2) 616; LARGE32-NEXT: lwz 5, L..C7@l(5) 617; LARGE32-NEXT: lwz 6, 4(5) 618; LARGE32-NEXT: lwz 5, 0(5) 619; LARGE32-NEXT: addc 4, 6, 4 620; LARGE32-NEXT: adde 3, 5, 3 621; LARGE32-NEXT: addi 1, 1, 32 622; LARGE32-NEXT: lwz 0, 8(1) 623; LARGE32-NEXT: mtlr 0 624; LARGE32-NEXT: blr 625; 626; SMALL64-LABEL: loadsTWInit: 627; SMALL64: # %bb.0: # %entry 628; SMALL64-NEXT: mflr 0 629; SMALL64-NEXT: stdu 1, -48(1) 630; SMALL64-NEXT: ld 3, L..C5(2) # target-flags(ppc-tlsgdm) @TWInit 631; SMALL64-NEXT: ld 4, L..C6(2) # target-flags(ppc-tlsgd) @TWInit 632; SMALL64-NEXT: std 0, 64(1) 633; SMALL64-NEXT: bla .__tls_get_addr[PR] 634; SMALL64-NEXT: ld 4, L..C7(2) # @GInit 635; SMALL64-NEXT: ld 3, 0(3) 636; SMALL64-NEXT: ld 4, 0(4) 637; SMALL64-NEXT: add 3, 4, 3 638; SMALL64-NEXT: addi 1, 1, 48 639; SMALL64-NEXT: ld 0, 16(1) 640; SMALL64-NEXT: mtlr 0 641; SMALL64-NEXT: blr 642; 643; LARGE64-LABEL: loadsTWInit: 644; LARGE64: # %bb.0: # %entry 645; LARGE64-NEXT: mflr 0 646; LARGE64-NEXT: stdu 1, -48(1) 647; LARGE64-NEXT: addis 3, L..C5@u(2) 648; LARGE64-NEXT: addis 4, L..C6@u(2) 649; LARGE64-NEXT: std 0, 64(1) 650; LARGE64-NEXT: ld 3, L..C5@l(3) 651; LARGE64-NEXT: ld 4, L..C6@l(4) 652; LARGE64-NEXT: bla .__tls_get_addr[PR] 653; LARGE64-NEXT: addis 4, L..C7@u(2) 654; LARGE64-NEXT: ld 3, 0(3) 655; LARGE64-NEXT: ld 4, L..C7@l(4) 656; LARGE64-NEXT: ld 4, 0(4) 657; LARGE64-NEXT: add 3, 4, 3 658; LARGE64-NEXT: addi 1, 1, 48 659; LARGE64-NEXT: ld 0, 16(1) 660; LARGE64-NEXT: mtlr 0 661; LARGE64-NEXT: blr 662entry: 663 %0 = load i64, ptr @TWInit, align 8 664 %1 = load i64, ptr @GInit, align 8 665 %add = add nsw i64 %1, %0 666 ret i64 %add 667} 668 669; External symbol reference checks for .__tls_get_addr/.__tls_get_mod 670 671; SMALL32: .extern .__tls_get_addr[PR] 672; SMALL32: .extern .__tls_get_mod[PR] 673; SMALL64: .extern .__tls_get_addr[PR] 674; SMALL64: .extern .__tls_get_mod[PR] 675; LARGE32: .extern .__tls_get_addr[PR] 676; LARGE32: .extern .__tls_get_mod[PR] 677; LARGE64: .extern .__tls_get_addr[PR] 678; LARGE64: .extern .__tls_get_mod[PR] 679 680; TOC entry checks 681 682; SMALL32-LABEL: .toc 683; SMALL32-LABEL: L..C0: 684; SMALL32-NEXT: .tc .TGInit[TC],TGInit[TL]@m 685; SMALL32-LABEL: L..C1: 686; SMALL32-NEXT: .tc TGInit[TC],TGInit[TL]@gd 687; SMALL32-LABEL: L..C2: 688; SMALL32-NEXT: .tc _Renamed..5f24__TLSML[TC],_Renamed..5f24__TLSML[TC]@ml 689; SMALL32-NEXT: .rename _Renamed..5f24__TLSML[TC],"_$TLSML" 690; SMALL32-LABEL: L..C3: 691; SMALL32-NEXT: .tc TIUninit[TC],TIUninit[UL]@ld 692; SMALL32-LABEL: L..C4: 693; SMALL32-NEXT: .tc TIInit[TC],TIInit[TL]@ld 694; SMALL32-LABEL: L..C5: 695; SMALL32-NEXT: .tc .TWInit[TC],TWInit[TL]@m 696; SMALL32-LABEL: L..C6: 697; SMALL32-NEXT: .tc TWInit[TC],TWInit[TL]@gd 698; SMALL32-LABEL: L..C7: 699; SMALL32-NEXT: .tc GInit[TC],GInit[RW] 700 701; LARGE32-LABEL: .toc 702; LARGE32-LABEL: L..C0: 703; LARGE32-NEXT: .tc .TGInit[TE],TGInit[TL]@m 704; LARGE32-LABEL: L..C1: 705; LARGE32-NEXT: .tc TGInit[TE],TGInit[TL]@gd 706; LARGE32-LABEL: L..C2: 707; LARGE32-NEXT: .tc TIUninit[TE],TIUninit[UL]@ld 708; LARGE32-LABEL: L..C3: 709; LARGE32-NEXT: .tc _Renamed..5f24__TLSML[TC],_Renamed..5f24__TLSML[TC]@ml 710; LARGE32-NEXT: .rename _Renamed..5f24__TLSML[TC],"_$TLSML" 711; LARGE32-LABEL: L..C4: 712; LARGE32-NEXT: .tc TIInit[TE],TIInit[TL]@ld 713; LARGE32-LABEL: L..C5: 714; LARGE32-NEXT: .tc .TWInit[TE],TWInit[TL]@m 715; LARGE32-LABEL: L..C6: 716; LARGE32-NEXT: .tc TWInit[TE],TWInit[TL]@gd 717; LARGE32-LABEL: L..C7: 718; LARGE32-NEXT: .tc GInit[TE],GInit[RW] 719 720; SMALL64-LABEL: .toc 721; SMALL64-LABEL: L..C0: 722; SMALL64-NEXT: .tc .TGInit[TC],TGInit[TL]@m 723; SMALL64-LABEL: L..C1: 724; SMALL64-NEXT: .tc TGInit[TC],TGInit[TL]@gd 725; SMALL64-LABEL: L..C2: 726; SMALL64-NEXT: .tc _Renamed..5f24__TLSML[TC],_Renamed..5f24__TLSML[TC]@ml 727; SMALL64-NEXT: .rename _Renamed..5f24__TLSML[TC],"_$TLSML" 728; SMALL64-LABEL: L..C3: 729; SMALL64-NEXT: .tc TIUninit[TC],TIUninit[UL]@ld 730; SMALL64-LABEL: L..C4: 731; SMALL64-NEXT: .tc TIInit[TC],TIInit[TL]@ld 732; SMALL64-LABEL: L..C5: 733; SMALL64-NEXT: .tc .TWInit[TC],TWInit[TL]@m 734; SMALL64-LABEL: L..C6: 735; SMALL64-NEXT: .tc TWInit[TC],TWInit[TL]@gd 736; SMALL64-LABEL: L..C7: 737; SMALL64-NEXT: .tc GInit[TC],GInit[RW] 738 739; LARGE64-LABEL: .toc 740; LARGE64-LABEL: L..C0: 741; LARGE64-NEXT: .tc .TGInit[TE],TGInit[TL]@m 742; LARGE64-LABEL: L..C1: 743; LARGE64-NEXT: .tc TGInit[TE],TGInit[TL]@gd 744; LARGE64-LABEL: L..C2: 745; LARGE64-NEXT: .tc _Renamed..5f24__TLSML[TC],_Renamed..5f24__TLSML[TC]@ml 746; LARGE64-NEXT: .rename _Renamed..5f24__TLSML[TC],"_$TLSML" 747; LARGE64-LABEL: L..C3: 748; LARGE64-NEXT: .tc TIUninit[TE],TIUninit[UL]@ld 749; LARGE64-LABEL: L..C4: 750; LARGE64-NEXT: .tc TIInit[TE],TIInit[TL]@ld 751; LARGE64-LABEL: L..C5: 752; LARGE64-NEXT: .tc .TWInit[TE],TWInit[TL]@m 753; LARGE64-LABEL: L..C6: 754; LARGE64-NEXT: .tc TWInit[TE],TWInit[TL]@gd 755; LARGE64-LABEL: L..C7: 756; LARGE64-NEXT: .tc GInit[TE],GInit[RW] 757 758attributes #0 = { nofree norecurse nounwind willreturn writeonly "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr4" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-float128,-htm,-mma,-paired-vector-memops,-power10-vector,-power8-vector,-power9-vector,-spe,-vsx" } 759attributes #1 = { norecurse nounwind readonly willreturn "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr4" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-float128,-htm,-mma,-paired-vector-memops,-power10-vector,-power8-vector,-power9-vector,-spe,-vsx" } 760