1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-ibm-aix-xcoff \ 3; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK-64,CHECK-64-OPT %s 4; RUN: llc -O0 -mcpu=pwr9 -mtriple=powerpc64-ibm-aix-xcoff \ 5; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK-64,CHECK-64-O0 %s 6; RUN: llc -mcpu=pwr9 -mtriple=powerpc-ibm-aix-xcoff \ 7; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-32,CHECK-32-OPT 8; RUN: llc -O0 -mcpu=pwr9 -mtriple=powerpc-ibm-aix-xcoff \ 9; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-32,CHECK-32-O0 10 11; The following testcases take one halfword element from the second vector and 12; inserts it at various locations in the first vector 13define <8 x i16> @shuffle_vector_halfword_0_8(<8 x i16> %a, <8 x i16> %b) { 14; CHECK-64-LABEL: shuffle_vector_halfword_0_8: 15; CHECK-64: # %bb.0: # %entry 16; CHECK-64-NEXT: vsldoi 3, 3, 3, 10 17; CHECK-64-NEXT: vinserth 2, 3, 0 18; CHECK-64-NEXT: blr 19; 20; CHECK-32-LABEL: shuffle_vector_halfword_0_8: 21; CHECK-32: # %bb.0: # %entry 22; CHECK-32-NEXT: vsldoi 3, 3, 3, 10 23; CHECK-32-NEXT: vinserth 2, 3, 0 24; CHECK-32-NEXT: blr 25entry: 26 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 27 ret <8 x i16> %vecins 28} 29 30define <8 x i16> @shuffle_vector_halfword_1_15(<8 x i16> %a, <8 x i16> %b) { 31; CHECK-64-LABEL: shuffle_vector_halfword_1_15: 32; CHECK-64: # %bb.0: # %entry 33; CHECK-64-NEXT: vsldoi 3, 3, 3, 8 34; CHECK-64-NEXT: vinserth 2, 3, 2 35; CHECK-64-NEXT: blr 36; 37; CHECK-32-LABEL: shuffle_vector_halfword_1_15: 38; CHECK-32: # %bb.0: # %entry 39; CHECK-32-NEXT: vsldoi 3, 3, 3, 8 40; CHECK-32-NEXT: vinserth 2, 3, 2 41; CHECK-32-NEXT: blr 42entry: 43 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 15, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 44 ret <8 x i16> %vecins 45} 46 47define <8 x i16> @shuffle_vector_halfword_2_9(<8 x i16> %a, <8 x i16> %b) { 48; CHECK-64-LABEL: shuffle_vector_halfword_2_9: 49; CHECK-64: # %bb.0: # %entry 50; CHECK-64-NEXT: vsldoi 3, 3, 3, 12 51; CHECK-64-NEXT: vinserth 2, 3, 4 52; CHECK-64-NEXT: blr 53; 54; CHECK-32-LABEL: shuffle_vector_halfword_2_9: 55; CHECK-32: # %bb.0: # %entry 56; CHECK-32-NEXT: vsldoi 3, 3, 3, 12 57; CHECK-32-NEXT: vinserth 2, 3, 4 58; CHECK-32-NEXT: blr 59entry: 60 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 9, i32 3, i32 4, i32 5, i32 6, i32 7> 61 ret <8 x i16> %vecins 62} 63 64define <8 x i16> @shuffle_vector_halfword_3_13(<8 x i16> %a, <8 x i16> %b) { 65; CHECK-64-LABEL: shuffle_vector_halfword_3_13: 66; CHECK-64: # %bb.0: # %entry 67; CHECK-64-NEXT: vsldoi 3, 3, 3, 4 68; CHECK-64-NEXT: vinserth 2, 3, 6 69; CHECK-64-NEXT: blr 70; 71; CHECK-32-LABEL: shuffle_vector_halfword_3_13: 72; CHECK-32: # %bb.0: # %entry 73; CHECK-32-NEXT: vsldoi 3, 3, 3, 4 74; CHECK-32-NEXT: vinserth 2, 3, 6 75; CHECK-32-NEXT: blr 76entry: 77 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 13, i32 4, i32 5, i32 6, i32 7> 78 ret <8 x i16> %vecins 79} 80 81define <8 x i16> @shuffle_vector_halfword_4_10(<8 x i16> %a, <8 x i16> %b) { 82; CHECK-64-LABEL: shuffle_vector_halfword_4_10: 83; CHECK-64: # %bb.0: # %entry 84; CHECK-64-NEXT: vsldoi 3, 3, 3, 14 85; CHECK-64-NEXT: vinserth 2, 3, 8 86; CHECK-64-NEXT: blr 87; 88; CHECK-32-LABEL: shuffle_vector_halfword_4_10: 89; CHECK-32: # %bb.0: # %entry 90; CHECK-32-NEXT: vsldoi 3, 3, 3, 14 91; CHECK-32-NEXT: vinserth 2, 3, 8 92; CHECK-32-NEXT: blr 93entry: 94 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 10, i32 5, i32 6, i32 7> 95 ret <8 x i16> %vecins 96} 97 98define <8 x i16> @shuffle_vector_halfword_5_14(<8 x i16> %a, <8 x i16> %b) { 99; CHECK-64-LABEL: shuffle_vector_halfword_5_14: 100; CHECK-64: # %bb.0: # %entry 101; CHECK-64-NEXT: vsldoi 3, 3, 3, 6 102; CHECK-64-NEXT: vinserth 2, 3, 10 103; CHECK-64-NEXT: blr 104; 105; CHECK-32-LABEL: shuffle_vector_halfword_5_14: 106; CHECK-32: # %bb.0: # %entry 107; CHECK-32-NEXT: vsldoi 3, 3, 3, 6 108; CHECK-32-NEXT: vinserth 2, 3, 10 109; CHECK-32-NEXT: blr 110entry: 111 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 14, i32 6, i32 7> 112 ret <8 x i16> %vecins 113} 114 115define <8 x i16> @shuffle_vector_halfword_6_11(<8 x i16> %a, <8 x i16> %b) { 116; CHECK-64-LABEL: shuffle_vector_halfword_6_11: 117; CHECK-64: # %bb.0: # %entry 118; CHECK-64-NEXT: vinserth 2, 3, 12 119; CHECK-64-NEXT: blr 120; 121; CHECK-32-LABEL: shuffle_vector_halfword_6_11: 122; CHECK-32: # %bb.0: # %entry 123; CHECK-32-NEXT: vinserth 2, 3, 12 124; CHECK-32-NEXT: blr 125entry: 126 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 11, i32 7> 127 ret <8 x i16> %vecins 128} 129 130define <8 x i16> @shuffle_vector_halfword_7_12(<8 x i16> %a, <8 x i16> %b) { 131; CHECK-64-LABEL: shuffle_vector_halfword_7_12: 132; CHECK-64: # %bb.0: # %entry 133; CHECK-64-NEXT: vsldoi 3, 3, 3, 2 134; CHECK-64-NEXT: vinserth 2, 3, 14 135; CHECK-64-NEXT: blr 136; 137; CHECK-32-LABEL: shuffle_vector_halfword_7_12: 138; CHECK-32: # %bb.0: # %entry 139; CHECK-32-NEXT: vsldoi 3, 3, 3, 2 140; CHECK-32-NEXT: vinserth 2, 3, 14 141; CHECK-32-NEXT: blr 142entry: 143 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 12> 144 ret <8 x i16> %vecins 145} 146 147define <8 x i16> @shuffle_vector_halfword_8_1(<8 x i16> %a, <8 x i16> %b) { 148; CHECK-64-OPT-LABEL: shuffle_vector_halfword_8_1: 149; CHECK-64-OPT: # %bb.0: # %entry 150; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 12 151; CHECK-64-OPT-NEXT: vinserth 3, 2, 0 152; CHECK-64-OPT-NEXT: vmr 2, 3 153; CHECK-64-OPT-NEXT: blr 154; 155; CHECK-64-O0-LABEL: shuffle_vector_halfword_8_1: 156; CHECK-64-O0: # %bb.0: # %entry 157; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 158; CHECK-64-O0-NEXT: vmr 3, 2 159; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 160; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 12 161; CHECK-64-O0-NEXT: vinserth 2, 3, 0 162; CHECK-64-O0-NEXT: blr 163; 164; CHECK-32-OPT-LABEL: shuffle_vector_halfword_8_1: 165; CHECK-32-OPT: # %bb.0: # %entry 166; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 12 167; CHECK-32-OPT-NEXT: vinserth 3, 2, 0 168; CHECK-32-OPT-NEXT: vmr 2, 3 169; CHECK-32-OPT-NEXT: blr 170; 171; CHECK-32-O0-LABEL: shuffle_vector_halfword_8_1: 172; CHECK-32-O0: # %bb.0: # %entry 173; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 174; CHECK-32-O0-NEXT: vmr 3, 2 175; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 176; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 12 177; CHECK-32-O0-NEXT: vinserth 2, 3, 0 178; CHECK-32-O0-NEXT: blr 179entry: 180 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 1, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 181 ret <8 x i16> %vecins 182} 183 184; The following testcases take one halfword element from the first vector and 185; inserts it at various locations in the second vector 186define <8 x i16> @shuffle_vector_halfword_9_7(<8 x i16> %a, <8 x i16> %b) { 187; CHECK-64-OPT-LABEL: shuffle_vector_halfword_9_7: 188; CHECK-64-OPT: # %bb.0: # %entry 189; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 8 190; CHECK-64-OPT-NEXT: vinserth 3, 2, 2 191; CHECK-64-OPT-NEXT: vmr 2, 3 192; CHECK-64-OPT-NEXT: blr 193; 194; CHECK-64-O0-LABEL: shuffle_vector_halfword_9_7: 195; CHECK-64-O0: # %bb.0: # %entry 196; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 197; CHECK-64-O0-NEXT: vmr 3, 2 198; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 199; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 8 200; CHECK-64-O0-NEXT: vinserth 2, 3, 2 201; CHECK-64-O0-NEXT: blr 202; 203; CHECK-32-OPT-LABEL: shuffle_vector_halfword_9_7: 204; CHECK-32-OPT: # %bb.0: # %entry 205; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 8 206; CHECK-32-OPT-NEXT: vinserth 3, 2, 2 207; CHECK-32-OPT-NEXT: vmr 2, 3 208; CHECK-32-OPT-NEXT: blr 209; 210; CHECK-32-O0-LABEL: shuffle_vector_halfword_9_7: 211; CHECK-32-O0: # %bb.0: # %entry 212; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 213; CHECK-32-O0-NEXT: vmr 3, 2 214; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 215; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 8 216; CHECK-32-O0-NEXT: vinserth 2, 3, 2 217; CHECK-32-O0-NEXT: blr 218entry: 219 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 7, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 220 ret <8 x i16> %vecins 221} 222 223define <8 x i16> @shuffle_vector_halfword_10_4(<8 x i16> %a, <8 x i16> %b) { 224; CHECK-64-OPT-LABEL: shuffle_vector_halfword_10_4: 225; CHECK-64-OPT: # %bb.0: # %entry 226; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 2 227; CHECK-64-OPT-NEXT: vinserth 3, 2, 4 228; CHECK-64-OPT-NEXT: vmr 2, 3 229; CHECK-64-OPT-NEXT: blr 230; 231; CHECK-64-O0-LABEL: shuffle_vector_halfword_10_4: 232; CHECK-64-O0: # %bb.0: # %entry 233; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 234; CHECK-64-O0-NEXT: vmr 3, 2 235; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 236; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 2 237; CHECK-64-O0-NEXT: vinserth 2, 3, 4 238; CHECK-64-O0-NEXT: blr 239; 240; CHECK-32-OPT-LABEL: shuffle_vector_halfword_10_4: 241; CHECK-32-OPT: # %bb.0: # %entry 242; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 2 243; CHECK-32-OPT-NEXT: vinserth 3, 2, 4 244; CHECK-32-OPT-NEXT: vmr 2, 3 245; CHECK-32-OPT-NEXT: blr 246; 247; CHECK-32-O0-LABEL: shuffle_vector_halfword_10_4: 248; CHECK-32-O0: # %bb.0: # %entry 249; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 250; CHECK-32-O0-NEXT: vmr 3, 2 251; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 252; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 2 253; CHECK-32-O0-NEXT: vinserth 2, 3, 4 254; CHECK-32-O0-NEXT: blr 255entry: 256 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 4, i32 11, i32 12, i32 13, i32 14, i32 15> 257 ret <8 x i16> %vecins 258} 259 260define <8 x i16> @shuffle_vector_halfword_11_2(<8 x i16> %a, <8 x i16> %b) { 261; CHECK-64-OPT-LABEL: shuffle_vector_halfword_11_2: 262; CHECK-64-OPT: # %bb.0: # %entry 263; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 14 264; CHECK-64-OPT-NEXT: vinserth 3, 2, 6 265; CHECK-64-OPT-NEXT: vmr 2, 3 266; CHECK-64-OPT-NEXT: blr 267; 268; CHECK-64-O0-LABEL: shuffle_vector_halfword_11_2: 269; CHECK-64-O0: # %bb.0: # %entry 270; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 271; CHECK-64-O0-NEXT: vmr 3, 2 272; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 273; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 14 274; CHECK-64-O0-NEXT: vinserth 2, 3, 6 275; CHECK-64-O0-NEXT: blr 276; 277; CHECK-32-OPT-LABEL: shuffle_vector_halfword_11_2: 278; CHECK-32-OPT: # %bb.0: # %entry 279; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 14 280; CHECK-32-OPT-NEXT: vinserth 3, 2, 6 281; CHECK-32-OPT-NEXT: vmr 2, 3 282; CHECK-32-OPT-NEXT: blr 283; 284; CHECK-32-O0-LABEL: shuffle_vector_halfword_11_2: 285; CHECK-32-O0: # %bb.0: # %entry 286; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 287; CHECK-32-O0-NEXT: vmr 3, 2 288; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 289; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 14 290; CHECK-32-O0-NEXT: vinserth 2, 3, 6 291; CHECK-32-O0-NEXT: blr 292entry: 293 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 2, i32 12, i32 13, i32 14, i32 15> 294 ret <8 x i16> %vecins 295} 296 297define <8 x i16> @shuffle_vector_halfword_12_6(<8 x i16> %a, <8 x i16> %b) { 298; CHECK-64-OPT-LABEL: shuffle_vector_halfword_12_6: 299; CHECK-64-OPT: # %bb.0: # %entry 300; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 6 301; CHECK-64-OPT-NEXT: vinserth 3, 2, 8 302; CHECK-64-OPT-NEXT: vmr 2, 3 303; CHECK-64-OPT-NEXT: blr 304; 305; CHECK-64-O0-LABEL: shuffle_vector_halfword_12_6: 306; CHECK-64-O0: # %bb.0: # %entry 307; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 308; CHECK-64-O0-NEXT: vmr 3, 2 309; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 310; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 6 311; CHECK-64-O0-NEXT: vinserth 2, 3, 8 312; CHECK-64-O0-NEXT: blr 313; 314; CHECK-32-OPT-LABEL: shuffle_vector_halfword_12_6: 315; CHECK-32-OPT: # %bb.0: # %entry 316; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 6 317; CHECK-32-OPT-NEXT: vinserth 3, 2, 8 318; CHECK-32-OPT-NEXT: vmr 2, 3 319; CHECK-32-OPT-NEXT: blr 320; 321; CHECK-32-O0-LABEL: shuffle_vector_halfword_12_6: 322; CHECK-32-O0: # %bb.0: # %entry 323; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 324; CHECK-32-O0-NEXT: vmr 3, 2 325; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 326; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 6 327; CHECK-32-O0-NEXT: vinserth 2, 3, 8 328; CHECK-32-O0-NEXT: blr 329entry: 330 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 6, i32 13, i32 14, i32 15> 331 ret <8 x i16> %vecins 332} 333 334define <8 x i16> @shuffle_vector_halfword_13_3(<8 x i16> %a, <8 x i16> %b) { 335; CHECK-64-OPT-LABEL: shuffle_vector_halfword_13_3: 336; CHECK-64-OPT: # %bb.0: # %entry 337; CHECK-64-OPT-NEXT: vinserth 3, 2, 10 338; CHECK-64-OPT-NEXT: vmr 2, 3 339; CHECK-64-OPT-NEXT: blr 340; 341; CHECK-64-O0-LABEL: shuffle_vector_halfword_13_3: 342; CHECK-64-O0: # %bb.0: # %entry 343; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 344; CHECK-64-O0-NEXT: vmr 3, 2 345; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 346; CHECK-64-O0-NEXT: vinserth 2, 3, 10 347; CHECK-64-O0-NEXT: blr 348; 349; CHECK-32-OPT-LABEL: shuffle_vector_halfword_13_3: 350; CHECK-32-OPT: # %bb.0: # %entry 351; CHECK-32-OPT-NEXT: vinserth 3, 2, 10 352; CHECK-32-OPT-NEXT: vmr 2, 3 353; CHECK-32-OPT-NEXT: blr 354; 355; CHECK-32-O0-LABEL: shuffle_vector_halfword_13_3: 356; CHECK-32-O0: # %bb.0: # %entry 357; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 358; CHECK-32-O0-NEXT: vmr 3, 2 359; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 360; CHECK-32-O0-NEXT: vinserth 2, 3, 10 361; CHECK-32-O0-NEXT: blr 362entry: 363 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 3, i32 14, i32 15> 364 ret <8 x i16> %vecins 365} 366 367define <8 x i16> @shuffle_vector_halfword_14_5(<8 x i16> %a, <8 x i16> %b) { 368; CHECK-64-OPT-LABEL: shuffle_vector_halfword_14_5: 369; CHECK-64-OPT: # %bb.0: # %entry 370; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 4 371; CHECK-64-OPT-NEXT: vinserth 3, 2, 12 372; CHECK-64-OPT-NEXT: vmr 2, 3 373; CHECK-64-OPT-NEXT: blr 374; 375; CHECK-64-O0-LABEL: shuffle_vector_halfword_14_5: 376; CHECK-64-O0: # %bb.0: # %entry 377; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 378; CHECK-64-O0-NEXT: vmr 3, 2 379; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 380; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 4 381; CHECK-64-O0-NEXT: vinserth 2, 3, 12 382; CHECK-64-O0-NEXT: blr 383; 384; CHECK-32-OPT-LABEL: shuffle_vector_halfword_14_5: 385; CHECK-32-OPT: # %bb.0: # %entry 386; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 4 387; CHECK-32-OPT-NEXT: vinserth 3, 2, 12 388; CHECK-32-OPT-NEXT: vmr 2, 3 389; CHECK-32-OPT-NEXT: blr 390; 391; CHECK-32-O0-LABEL: shuffle_vector_halfword_14_5: 392; CHECK-32-O0: # %bb.0: # %entry 393; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 394; CHECK-32-O0-NEXT: vmr 3, 2 395; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 396; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 4 397; CHECK-32-O0-NEXT: vinserth 2, 3, 12 398; CHECK-32-O0-NEXT: blr 399entry: 400 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 5, i32 15> 401 ret <8 x i16> %vecins 402} 403 404define <8 x i16> @shuffle_vector_halfword_15_0(<8 x i16> %a, <8 x i16> %b) { 405; CHECK-64-OPT-LABEL: shuffle_vector_halfword_15_0: 406; CHECK-64-OPT: # %bb.0: # %entry 407; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 10 408; CHECK-64-OPT-NEXT: vinserth 3, 2, 14 409; CHECK-64-OPT-NEXT: vmr 2, 3 410; CHECK-64-OPT-NEXT: blr 411; 412; CHECK-64-O0-LABEL: shuffle_vector_halfword_15_0: 413; CHECK-64-O0: # %bb.0: # %entry 414; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 415; CHECK-64-O0-NEXT: vmr 3, 2 416; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 417; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 10 418; CHECK-64-O0-NEXT: vinserth 2, 3, 14 419; CHECK-64-O0-NEXT: blr 420; 421; CHECK-32-OPT-LABEL: shuffle_vector_halfword_15_0: 422; CHECK-32-OPT: # %bb.0: # %entry 423; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 10 424; CHECK-32-OPT-NEXT: vinserth 3, 2, 14 425; CHECK-32-OPT-NEXT: vmr 2, 3 426; CHECK-32-OPT-NEXT: blr 427; 428; CHECK-32-O0-LABEL: shuffle_vector_halfword_15_0: 429; CHECK-32-O0: # %bb.0: # %entry 430; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 431; CHECK-32-O0-NEXT: vmr 3, 2 432; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 433; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 10 434; CHECK-32-O0-NEXT: vinserth 2, 3, 14 435; CHECK-32-O0-NEXT: blr 436entry: 437 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 0> 438 ret <8 x i16> %vecins 439} 440 441; The following testcases use the same vector in both arguments of the 442; shufflevector. If halfword element 3 in BE mode(or 4 in LE mode) is the one 443; we're attempting to insert, then we can use the vector insert instruction 444define <8 x i16> @shuffle_vector_halfword_0_4(<8 x i16> %a) { 445; CHECK-64-LABEL: shuffle_vector_halfword_0_4: 446; CHECK-64: # %bb.0: # %entry 447; CHECK-64-NEXT: ld 3, L..C0(2) # %const.0 448; CHECK-64-NEXT: lxv 0, 0(3) 449; CHECK-64-NEXT: xxperm 34, 34, 0 450; CHECK-64-NEXT: blr 451; 452; CHECK-32-LABEL: shuffle_vector_halfword_0_4: 453; CHECK-32: # %bb.0: # %entry 454; CHECK-32-NEXT: lwz 3, L..C0(2) # %const.0 455; CHECK-32-NEXT: lxv 0, 0(3) 456; CHECK-32-NEXT: xxperm 34, 34, 0 457; CHECK-32-NEXT: blr 458entry: 459 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 4, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 460 ret <8 x i16> %vecins 461} 462 463define <8 x i16> @shuffle_vector_halfword_1_3(<8 x i16> %a) { 464; CHECK-64-LABEL: shuffle_vector_halfword_1_3: 465; CHECK-64: # %bb.0: # %entry 466; CHECK-64-NEXT: vinserth 2, 2, 2 467; CHECK-64-NEXT: blr 468; 469; CHECK-32-LABEL: shuffle_vector_halfword_1_3: 470; CHECK-32: # %bb.0: # %entry 471; CHECK-32-NEXT: vinserth 2, 2, 2 472; CHECK-32-NEXT: blr 473entry: 474 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 3, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 475 ret <8 x i16> %vecins 476} 477 478define <8 x i16> @shuffle_vector_halfword_2_3(<8 x i16> %a) { 479; CHECK-64-LABEL: shuffle_vector_halfword_2_3: 480; CHECK-64: # %bb.0: # %entry 481; CHECK-64-NEXT: vinserth 2, 2, 4 482; CHECK-64-NEXT: blr 483; 484; CHECK-32-LABEL: shuffle_vector_halfword_2_3: 485; CHECK-32: # %bb.0: # %entry 486; CHECK-32-NEXT: vinserth 2, 2, 4 487; CHECK-32-NEXT: blr 488entry: 489 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 3, i32 3, i32 4, i32 5, i32 6, i32 7> 490 ret <8 x i16> %vecins 491} 492 493define <8 x i16> @shuffle_vector_halfword_3_4(<8 x i16> %a) { 494; CHECK-64-LABEL: shuffle_vector_halfword_3_4: 495; CHECK-64: # %bb.0: # %entry 496; CHECK-64-NEXT: ld 3, L..C1(2) # %const.0 497; CHECK-64-NEXT: lxv 0, 0(3) 498; CHECK-64-NEXT: xxperm 34, 34, 0 499; CHECK-64-NEXT: blr 500; 501; CHECK-32-LABEL: shuffle_vector_halfword_3_4: 502; CHECK-32: # %bb.0: # %entry 503; CHECK-32-NEXT: lwz 3, L..C1(2) # %const.0 504; CHECK-32-NEXT: lxv 0, 0(3) 505; CHECK-32-NEXT: xxperm 34, 34, 0 506; CHECK-32-NEXT: blr 507entry: 508 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 4, i32 4, i32 5, i32 6, i32 7> 509 ret <8 x i16> %vecins 510} 511 512define <8 x i16> @shuffle_vector_halfword_4_3(<8 x i16> %a) { 513; CHECK-64-LABEL: shuffle_vector_halfword_4_3: 514; CHECK-64: # %bb.0: # %entry 515; CHECK-64-NEXT: vinserth 2, 2, 8 516; CHECK-64-NEXT: blr 517; 518; CHECK-32-LABEL: shuffle_vector_halfword_4_3: 519; CHECK-32: # %bb.0: # %entry 520; CHECK-32-NEXT: vinserth 2, 2, 8 521; CHECK-32-NEXT: blr 522entry: 523 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 3, i32 5, i32 6, i32 7> 524 ret <8 x i16> %vecins 525} 526 527define <8 x i16> @shuffle_vector_halfword_5_3(<8 x i16> %a) { 528; CHECK-64-LABEL: shuffle_vector_halfword_5_3: 529; CHECK-64: # %bb.0: # %entry 530; CHECK-64-NEXT: vinserth 2, 2, 10 531; CHECK-64-NEXT: blr 532; 533; CHECK-32-LABEL: shuffle_vector_halfword_5_3: 534; CHECK-32: # %bb.0: # %entry 535; CHECK-32-NEXT: vinserth 2, 2, 10 536; CHECK-32-NEXT: blr 537entry: 538 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 3, i32 6, i32 7> 539 ret <8 x i16> %vecins 540} 541 542define <8 x i16> @shuffle_vector_halfword_6_4(<8 x i16> %a) { 543; CHECK-64-LABEL: shuffle_vector_halfword_6_4: 544; CHECK-64: # %bb.0: # %entry 545; CHECK-64-NEXT: ld 3, L..C2(2) # %const.0 546; CHECK-64-NEXT: lxv 0, 0(3) 547; CHECK-64-NEXT: xxperm 34, 34, 0 548; CHECK-64-NEXT: blr 549; 550; CHECK-32-LABEL: shuffle_vector_halfword_6_4: 551; CHECK-32: # %bb.0: # %entry 552; CHECK-32-NEXT: lwz 3, L..C2(2) # %const.0 553; CHECK-32-NEXT: lxv 0, 0(3) 554; CHECK-32-NEXT: xxperm 34, 34, 0 555; CHECK-32-NEXT: blr 556entry: 557 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 4, i32 7> 558 ret <8 x i16> %vecins 559} 560 561define <8 x i16> @shuffle_vector_halfword_7_4(<8 x i16> %a) { 562; CHECK-64-LABEL: shuffle_vector_halfword_7_4: 563; CHECK-64: # %bb.0: # %entry 564; CHECK-64-NEXT: ld 3, L..C3(2) # %const.0 565; CHECK-64-NEXT: lxv 0, 0(3) 566; CHECK-64-NEXT: xxperm 34, 34, 0 567; CHECK-64-NEXT: blr 568; 569; CHECK-32-LABEL: shuffle_vector_halfword_7_4: 570; CHECK-32: # %bb.0: # %entry 571; CHECK-32-NEXT: lwz 3, L..C3(2) # %const.0 572; CHECK-32-NEXT: lxv 0, 0(3) 573; CHECK-32-NEXT: xxperm 34, 34, 0 574; CHECK-32-NEXT: blr 575entry: 576 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 4> 577 ret <8 x i16> %vecins 578} 579 580; The following testcases take one byte element from the second vector and 581; inserts it at various locations in the first vector 582define <16 x i8> @shuffle_vector_byte_0_16(<16 x i8> %a, <16 x i8> %b) { 583; CHECK-64-LABEL: shuffle_vector_byte_0_16: 584; CHECK-64: # %bb.0: # %entry 585; CHECK-64-NEXT: vsldoi 3, 3, 3, 9 586; CHECK-64-NEXT: vinsertb 2, 3, 0 587; CHECK-64-NEXT: blr 588; 589; CHECK-32-LABEL: shuffle_vector_byte_0_16: 590; CHECK-32: # %bb.0: # %entry 591; CHECK-32-NEXT: vsldoi 3, 3, 3, 9 592; CHECK-32-NEXT: vinsertb 2, 3, 0 593; CHECK-32-NEXT: blr 594entry: 595 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 596 ret <16 x i8> %vecins 597} 598 599define <16 x i8> @shuffle_vector_byte_1_25(<16 x i8> %a, <16 x i8> %b) { 600; CHECK-64-LABEL: shuffle_vector_byte_1_25: 601; CHECK-64: # %bb.0: # %entry 602; CHECK-64-NEXT: vsldoi 3, 3, 3, 2 603; CHECK-64-NEXT: vinsertb 2, 3, 1 604; CHECK-64-NEXT: blr 605; 606; CHECK-32-LABEL: shuffle_vector_byte_1_25: 607; CHECK-32: # %bb.0: # %entry 608; CHECK-32-NEXT: vsldoi 3, 3, 3, 2 609; CHECK-32-NEXT: vinsertb 2, 3, 1 610; CHECK-32-NEXT: blr 611entry: 612 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 25, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 613 ret <16 x i8> %vecins 614} 615 616define <16 x i8> @shuffle_vector_byte_2_18(<16 x i8> %a, <16 x i8> %b) { 617; CHECK-64-LABEL: shuffle_vector_byte_2_18: 618; CHECK-64: # %bb.0: # %entry 619; CHECK-64-NEXT: vsldoi 3, 3, 3, 11 620; CHECK-64-NEXT: vinsertb 2, 3, 2 621; CHECK-64-NEXT: blr 622; 623; CHECK-32-LABEL: shuffle_vector_byte_2_18: 624; CHECK-32: # %bb.0: # %entry 625; CHECK-32-NEXT: vsldoi 3, 3, 3, 11 626; CHECK-32-NEXT: vinsertb 2, 3, 2 627; CHECK-32-NEXT: blr 628entry: 629 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 18, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 630 ret <16 x i8> %vecins 631} 632 633define <16 x i8> @shuffle_vector_byte_3_27(<16 x i8> %a, <16 x i8> %b) { 634; CHECK-64-LABEL: shuffle_vector_byte_3_27: 635; CHECK-64: # %bb.0: # %entry 636; CHECK-64-NEXT: vsldoi 3, 3, 3, 4 637; CHECK-64-NEXT: vinsertb 2, 3, 3 638; CHECK-64-NEXT: blr 639; 640; CHECK-32-LABEL: shuffle_vector_byte_3_27: 641; CHECK-32: # %bb.0: # %entry 642; CHECK-32-NEXT: vsldoi 3, 3, 3, 4 643; CHECK-32-NEXT: vinsertb 2, 3, 3 644; CHECK-32-NEXT: blr 645entry: 646 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 27, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 647 ret <16 x i8> %vecins 648} 649 650define <16 x i8> @shuffle_vector_byte_4_20(<16 x i8> %a, <16 x i8> %b) { 651; CHECK-64-LABEL: shuffle_vector_byte_4_20: 652; CHECK-64: # %bb.0: # %entry 653; CHECK-64-NEXT: vsldoi 3, 3, 3, 13 654; CHECK-64-NEXT: vinsertb 2, 3, 4 655; CHECK-64-NEXT: blr 656; 657; CHECK-32-LABEL: shuffle_vector_byte_4_20: 658; CHECK-32: # %bb.0: # %entry 659; CHECK-32-NEXT: vsldoi 3, 3, 3, 13 660; CHECK-32-NEXT: vinsertb 2, 3, 4 661; CHECK-32-NEXT: blr 662entry: 663 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 664 ret <16 x i8> %vecins 665} 666 667define <16 x i8> @shuffle_vector_byte_5_29(<16 x i8> %a, <16 x i8> %b) { 668; CHECK-64-LABEL: shuffle_vector_byte_5_29: 669; CHECK-64: # %bb.0: # %entry 670; CHECK-64-NEXT: vsldoi 3, 3, 3, 6 671; CHECK-64-NEXT: vinsertb 2, 3, 5 672; CHECK-64-NEXT: blr 673; 674; CHECK-32-LABEL: shuffle_vector_byte_5_29: 675; CHECK-32: # %bb.0: # %entry 676; CHECK-32-NEXT: vsldoi 3, 3, 3, 6 677; CHECK-32-NEXT: vinsertb 2, 3, 5 678; CHECK-32-NEXT: blr 679entry: 680 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 29, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 681 ret <16 x i8> %vecins 682} 683 684define <16 x i8> @shuffle_vector_byte_6_22(<16 x i8> %a, <16 x i8> %b) { 685; CHECK-64-LABEL: shuffle_vector_byte_6_22: 686; CHECK-64: # %bb.0: # %entry 687; CHECK-64-NEXT: vsldoi 3, 3, 3, 15 688; CHECK-64-NEXT: vinsertb 2, 3, 6 689; CHECK-64-NEXT: blr 690; 691; CHECK-32-LABEL: shuffle_vector_byte_6_22: 692; CHECK-32: # %bb.0: # %entry 693; CHECK-32-NEXT: vsldoi 3, 3, 3, 15 694; CHECK-32-NEXT: vinsertb 2, 3, 6 695; CHECK-32-NEXT: blr 696entry: 697 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 22, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 698 ret <16 x i8> %vecins 699} 700 701define <16 x i8> @shuffle_vector_byte_7_31(<16 x i8> %a, <16 x i8> %b) { 702; CHECK-64-LABEL: shuffle_vector_byte_7_31: 703; CHECK-64: # %bb.0: # %entry 704; CHECK-64-NEXT: vsldoi 3, 3, 3, 8 705; CHECK-64-NEXT: vinsertb 2, 3, 7 706; CHECK-64-NEXT: blr 707; 708; CHECK-32-LABEL: shuffle_vector_byte_7_31: 709; CHECK-32: # %bb.0: # %entry 710; CHECK-32-NEXT: vsldoi 3, 3, 3, 8 711; CHECK-32-NEXT: vinsertb 2, 3, 7 712; CHECK-32-NEXT: blr 713entry: 714 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 31, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 715 ret <16 x i8> %vecins 716} 717 718define <16 x i8> @shuffle_vector_byte_8_24(<16 x i8> %a, <16 x i8> %b) { 719; CHECK-64-LABEL: shuffle_vector_byte_8_24: 720; CHECK-64: # %bb.0: # %entry 721; CHECK-64-NEXT: vsldoi 3, 3, 3, 1 722; CHECK-64-NEXT: vinsertb 2, 3, 8 723; CHECK-64-NEXT: blr 724; 725; CHECK-32-LABEL: shuffle_vector_byte_8_24: 726; CHECK-32: # %bb.0: # %entry 727; CHECK-32-NEXT: vsldoi 3, 3, 3, 1 728; CHECK-32-NEXT: vinsertb 2, 3, 8 729; CHECK-32-NEXT: blr 730entry: 731 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 24, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 732 ret <16 x i8> %vecins 733} 734 735define <16 x i8> @shuffle_vector_byte_9_17(<16 x i8> %a, <16 x i8> %b) { 736; CHECK-64-LABEL: shuffle_vector_byte_9_17: 737; CHECK-64: # %bb.0: # %entry 738; CHECK-64-NEXT: vsldoi 3, 3, 3, 10 739; CHECK-64-NEXT: vinsertb 2, 3, 9 740; CHECK-64-NEXT: blr 741; 742; CHECK-32-LABEL: shuffle_vector_byte_9_17: 743; CHECK-32: # %bb.0: # %entry 744; CHECK-32-NEXT: vsldoi 3, 3, 3, 10 745; CHECK-32-NEXT: vinsertb 2, 3, 9 746; CHECK-32-NEXT: blr 747entry: 748 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 17, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 749 ret <16 x i8> %vecins 750} 751 752define <16 x i8> @shuffle_vector_byte_10_26(<16 x i8> %a, <16 x i8> %b) { 753; CHECK-64-LABEL: shuffle_vector_byte_10_26: 754; CHECK-64: # %bb.0: # %entry 755; CHECK-64-NEXT: vsldoi 3, 3, 3, 3 756; CHECK-64-NEXT: vinsertb 2, 3, 10 757; CHECK-64-NEXT: blr 758; 759; CHECK-32-LABEL: shuffle_vector_byte_10_26: 760; CHECK-32: # %bb.0: # %entry 761; CHECK-32-NEXT: vsldoi 3, 3, 3, 3 762; CHECK-32-NEXT: vinsertb 2, 3, 10 763; CHECK-32-NEXT: blr 764entry: 765 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 26, i32 11, i32 12, i32 13, i32 14, i32 15> 766 ret <16 x i8> %vecins 767} 768 769define <16 x i8> @shuffle_vector_byte_11_19(<16 x i8> %a, <16 x i8> %b) { 770; CHECK-64-LABEL: shuffle_vector_byte_11_19: 771; CHECK-64: # %bb.0: # %entry 772; CHECK-64-NEXT: vsldoi 3, 3, 3, 12 773; CHECK-64-NEXT: vinsertb 2, 3, 11 774; CHECK-64-NEXT: blr 775; 776; CHECK-32-LABEL: shuffle_vector_byte_11_19: 777; CHECK-32: # %bb.0: # %entry 778; CHECK-32-NEXT: vsldoi 3, 3, 3, 12 779; CHECK-32-NEXT: vinsertb 2, 3, 11 780; CHECK-32-NEXT: blr 781entry: 782 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 19, i32 12, i32 13, i32 14, i32 15> 783 ret <16 x i8> %vecins 784} 785 786define <16 x i8> @shuffle_vector_byte_12_28(<16 x i8> %a, <16 x i8> %b) { 787; CHECK-64-LABEL: shuffle_vector_byte_12_28: 788; CHECK-64: # %bb.0: # %entry 789; CHECK-64-NEXT: vsldoi 3, 3, 3, 5 790; CHECK-64-NEXT: vinsertb 2, 3, 12 791; CHECK-64-NEXT: blr 792; 793; CHECK-32-LABEL: shuffle_vector_byte_12_28: 794; CHECK-32: # %bb.0: # %entry 795; CHECK-32-NEXT: vsldoi 3, 3, 3, 5 796; CHECK-32-NEXT: vinsertb 2, 3, 12 797; CHECK-32-NEXT: blr 798entry: 799 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 28, i32 13, i32 14, i32 15> 800 ret <16 x i8> %vecins 801} 802 803define <16 x i8> @shuffle_vector_byte_13_21(<16 x i8> %a, <16 x i8> %b) { 804; CHECK-64-LABEL: shuffle_vector_byte_13_21: 805; CHECK-64: # %bb.0: # %entry 806; CHECK-64-NEXT: vsldoi 3, 3, 3, 14 807; CHECK-64-NEXT: vinsertb 2, 3, 13 808; CHECK-64-NEXT: blr 809; 810; CHECK-32-LABEL: shuffle_vector_byte_13_21: 811; CHECK-32: # %bb.0: # %entry 812; CHECK-32-NEXT: vsldoi 3, 3, 3, 14 813; CHECK-32-NEXT: vinsertb 2, 3, 13 814; CHECK-32-NEXT: blr 815entry: 816 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 21, i32 14, i32 15> 817 ret <16 x i8> %vecins 818} 819 820define <16 x i8> @shuffle_vector_byte_14_30(<16 x i8> %a, <16 x i8> %b) { 821; CHECK-64-LABEL: shuffle_vector_byte_14_30: 822; CHECK-64: # %bb.0: # %entry 823; CHECK-64-NEXT: vsldoi 3, 3, 3, 7 824; CHECK-64-NEXT: vinsertb 2, 3, 14 825; CHECK-64-NEXT: blr 826; 827; CHECK-32-LABEL: shuffle_vector_byte_14_30: 828; CHECK-32: # %bb.0: # %entry 829; CHECK-32-NEXT: vsldoi 3, 3, 3, 7 830; CHECK-32-NEXT: vinsertb 2, 3, 14 831; CHECK-32-NEXT: blr 832entry: 833 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 30, i32 15> 834 ret <16 x i8> %vecins 835} 836 837define <16 x i8> @shuffle_vector_byte_15_23(<16 x i8> %a, <16 x i8> %b) { 838; CHECK-64-LABEL: shuffle_vector_byte_15_23: 839; CHECK-64: # %bb.0: # %entry 840; CHECK-64-NEXT: vinsertb 2, 3, 15 841; CHECK-64-NEXT: blr 842; 843; CHECK-32-LABEL: shuffle_vector_byte_15_23: 844; CHECK-32: # %bb.0: # %entry 845; CHECK-32-NEXT: vinsertb 2, 3, 15 846; CHECK-32-NEXT: blr 847entry: 848 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 23> 849 ret <16 x i8> %vecins 850} 851 852; The following testcases take one byte element from the first vector and 853; inserts it at various locations in the second vector 854define <16 x i8> @shuffle_vector_byte_16_8(<16 x i8> %a, <16 x i8> %b) { 855; CHECK-64-OPT-LABEL: shuffle_vector_byte_16_8: 856; CHECK-64-OPT: # %bb.0: # %entry 857; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 1 858; CHECK-64-OPT-NEXT: vinsertb 3, 2, 0 859; CHECK-64-OPT-NEXT: vmr 2, 3 860; CHECK-64-OPT-NEXT: blr 861; 862; CHECK-64-O0-LABEL: shuffle_vector_byte_16_8: 863; CHECK-64-O0: # %bb.0: # %entry 864; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 865; CHECK-64-O0-NEXT: vmr 3, 2 866; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 867; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 1 868; CHECK-64-O0-NEXT: vinsertb 2, 3, 0 869; CHECK-64-O0-NEXT: blr 870; 871; CHECK-32-OPT-LABEL: shuffle_vector_byte_16_8: 872; CHECK-32-OPT: # %bb.0: # %entry 873; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 1 874; CHECK-32-OPT-NEXT: vinsertb 3, 2, 0 875; CHECK-32-OPT-NEXT: vmr 2, 3 876; CHECK-32-OPT-NEXT: blr 877; 878; CHECK-32-O0-LABEL: shuffle_vector_byte_16_8: 879; CHECK-32-O0: # %bb.0: # %entry 880; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 881; CHECK-32-O0-NEXT: vmr 3, 2 882; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 883; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 1 884; CHECK-32-O0-NEXT: vinsertb 2, 3, 0 885; CHECK-32-O0-NEXT: blr 886entry: 887 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 8, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> 888 ret <16 x i8> %vecins 889} 890 891define <16 x i8> @shuffle_vector_byte_17_1(<16 x i8> %a, <16 x i8> %b) { 892; CHECK-64-OPT-LABEL: shuffle_vector_byte_17_1: 893; CHECK-64-OPT: # %bb.0: # %entry 894; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 10 895; CHECK-64-OPT-NEXT: vinsertb 3, 2, 1 896; CHECK-64-OPT-NEXT: vmr 2, 3 897; CHECK-64-OPT-NEXT: blr 898; 899; CHECK-64-O0-LABEL: shuffle_vector_byte_17_1: 900; CHECK-64-O0: # %bb.0: # %entry 901; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 902; CHECK-64-O0-NEXT: vmr 3, 2 903; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 904; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 10 905; CHECK-64-O0-NEXT: vinsertb 2, 3, 1 906; CHECK-64-O0-NEXT: blr 907; 908; CHECK-32-OPT-LABEL: shuffle_vector_byte_17_1: 909; CHECK-32-OPT: # %bb.0: # %entry 910; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 10 911; CHECK-32-OPT-NEXT: vinsertb 3, 2, 1 912; CHECK-32-OPT-NEXT: vmr 2, 3 913; CHECK-32-OPT-NEXT: blr 914; 915; CHECK-32-O0-LABEL: shuffle_vector_byte_17_1: 916; CHECK-32-O0: # %bb.0: # %entry 917; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 918; CHECK-32-O0-NEXT: vmr 3, 2 919; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 920; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 10 921; CHECK-32-O0-NEXT: vinsertb 2, 3, 1 922; CHECK-32-O0-NEXT: blr 923entry: 924 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 1, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> 925 ret <16 x i8> %vecins 926} 927 928define <16 x i8> @shuffle_vector_byte_18_10(<16 x i8> %a, <16 x i8> %b) { 929; CHECK-64-OPT-LABEL: shuffle_vector_byte_18_10: 930; CHECK-64-OPT: # %bb.0: # %entry 931; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 3 932; CHECK-64-OPT-NEXT: vinsertb 3, 2, 2 933; CHECK-64-OPT-NEXT: vmr 2, 3 934; CHECK-64-OPT-NEXT: blr 935; 936; CHECK-64-O0-LABEL: shuffle_vector_byte_18_10: 937; CHECK-64-O0: # %bb.0: # %entry 938; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 939; CHECK-64-O0-NEXT: vmr 3, 2 940; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 941; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 3 942; CHECK-64-O0-NEXT: vinsertb 2, 3, 2 943; CHECK-64-O0-NEXT: blr 944; 945; CHECK-32-OPT-LABEL: shuffle_vector_byte_18_10: 946; CHECK-32-OPT: # %bb.0: # %entry 947; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 3 948; CHECK-32-OPT-NEXT: vinsertb 3, 2, 2 949; CHECK-32-OPT-NEXT: vmr 2, 3 950; CHECK-32-OPT-NEXT: blr 951; 952; CHECK-32-O0-LABEL: shuffle_vector_byte_18_10: 953; CHECK-32-O0: # %bb.0: # %entry 954; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 955; CHECK-32-O0-NEXT: vmr 3, 2 956; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 957; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 3 958; CHECK-32-O0-NEXT: vinsertb 2, 3, 2 959; CHECK-32-O0-NEXT: blr 960entry: 961 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 10, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> 962 ret <16 x i8> %vecins 963} 964 965define <16 x i8> @shuffle_vector_byte_19_3(<16 x i8> %a, <16 x i8> %b) { 966; CHECK-64-OPT-LABEL: shuffle_vector_byte_19_3: 967; CHECK-64-OPT: # %bb.0: # %entry 968; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 12 969; CHECK-64-OPT-NEXT: vinsertb 3, 2, 3 970; CHECK-64-OPT-NEXT: vmr 2, 3 971; CHECK-64-OPT-NEXT: blr 972; 973; CHECK-64-O0-LABEL: shuffle_vector_byte_19_3: 974; CHECK-64-O0: # %bb.0: # %entry 975; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 976; CHECK-64-O0-NEXT: vmr 3, 2 977; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 978; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 12 979; CHECK-64-O0-NEXT: vinsertb 2, 3, 3 980; CHECK-64-O0-NEXT: blr 981; 982; CHECK-32-OPT-LABEL: shuffle_vector_byte_19_3: 983; CHECK-32-OPT: # %bb.0: # %entry 984; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 12 985; CHECK-32-OPT-NEXT: vinsertb 3, 2, 3 986; CHECK-32-OPT-NEXT: vmr 2, 3 987; CHECK-32-OPT-NEXT: blr 988; 989; CHECK-32-O0-LABEL: shuffle_vector_byte_19_3: 990; CHECK-32-O0: # %bb.0: # %entry 991; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 992; CHECK-32-O0-NEXT: vmr 3, 2 993; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 994; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 12 995; CHECK-32-O0-NEXT: vinsertb 2, 3, 3 996; CHECK-32-O0-NEXT: blr 997entry: 998 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 3, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> 999 ret <16 x i8> %vecins 1000} 1001 1002define <16 x i8> @shuffle_vector_byte_20_12(<16 x i8> %a, <16 x i8> %b) { 1003; CHECK-64-OPT-LABEL: shuffle_vector_byte_20_12: 1004; CHECK-64-OPT: # %bb.0: # %entry 1005; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 5 1006; CHECK-64-OPT-NEXT: vinsertb 3, 2, 4 1007; CHECK-64-OPT-NEXT: vmr 2, 3 1008; CHECK-64-OPT-NEXT: blr 1009; 1010; CHECK-64-O0-LABEL: shuffle_vector_byte_20_12: 1011; CHECK-64-O0: # %bb.0: # %entry 1012; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 1013; CHECK-64-O0-NEXT: vmr 3, 2 1014; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 1015; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 5 1016; CHECK-64-O0-NEXT: vinsertb 2, 3, 4 1017; CHECK-64-O0-NEXT: blr 1018; 1019; CHECK-32-OPT-LABEL: shuffle_vector_byte_20_12: 1020; CHECK-32-OPT: # %bb.0: # %entry 1021; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 5 1022; CHECK-32-OPT-NEXT: vinsertb 3, 2, 4 1023; CHECK-32-OPT-NEXT: vmr 2, 3 1024; CHECK-32-OPT-NEXT: blr 1025; 1026; CHECK-32-O0-LABEL: shuffle_vector_byte_20_12: 1027; CHECK-32-O0: # %bb.0: # %entry 1028; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 1029; CHECK-32-O0-NEXT: vmr 3, 2 1030; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 1031; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 5 1032; CHECK-32-O0-NEXT: vinsertb 2, 3, 4 1033; CHECK-32-O0-NEXT: blr 1034entry: 1035 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 12, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> 1036 ret <16 x i8> %vecins 1037} 1038 1039define <16 x i8> @shuffle_vector_byte_21_5(<16 x i8> %a, <16 x i8> %b) { 1040; CHECK-64-OPT-LABEL: shuffle_vector_byte_21_5: 1041; CHECK-64-OPT: # %bb.0: # %entry 1042; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 14 1043; CHECK-64-OPT-NEXT: vinsertb 3, 2, 5 1044; CHECK-64-OPT-NEXT: vmr 2, 3 1045; CHECK-64-OPT-NEXT: blr 1046; 1047; CHECK-64-O0-LABEL: shuffle_vector_byte_21_5: 1048; CHECK-64-O0: # %bb.0: # %entry 1049; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 1050; CHECK-64-O0-NEXT: vmr 3, 2 1051; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 1052; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 14 1053; CHECK-64-O0-NEXT: vinsertb 2, 3, 5 1054; CHECK-64-O0-NEXT: blr 1055; 1056; CHECK-32-OPT-LABEL: shuffle_vector_byte_21_5: 1057; CHECK-32-OPT: # %bb.0: # %entry 1058; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 14 1059; CHECK-32-OPT-NEXT: vinsertb 3, 2, 5 1060; CHECK-32-OPT-NEXT: vmr 2, 3 1061; CHECK-32-OPT-NEXT: blr 1062; 1063; CHECK-32-O0-LABEL: shuffle_vector_byte_21_5: 1064; CHECK-32-O0: # %bb.0: # %entry 1065; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 1066; CHECK-32-O0-NEXT: vmr 3, 2 1067; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 1068; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 14 1069; CHECK-32-O0-NEXT: vinsertb 2, 3, 5 1070; CHECK-32-O0-NEXT: blr 1071entry: 1072 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 5, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> 1073 ret <16 x i8> %vecins 1074} 1075 1076define <16 x i8> @shuffle_vector_byte_22_14(<16 x i8> %a, <16 x i8> %b) { 1077; CHECK-64-OPT-LABEL: shuffle_vector_byte_22_14: 1078; CHECK-64-OPT: # %bb.0: # %entry 1079; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 7 1080; CHECK-64-OPT-NEXT: vinsertb 3, 2, 6 1081; CHECK-64-OPT-NEXT: vmr 2, 3 1082; CHECK-64-OPT-NEXT: blr 1083; 1084; CHECK-64-O0-LABEL: shuffle_vector_byte_22_14: 1085; CHECK-64-O0: # %bb.0: # %entry 1086; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 1087; CHECK-64-O0-NEXT: vmr 3, 2 1088; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 1089; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 7 1090; CHECK-64-O0-NEXT: vinsertb 2, 3, 6 1091; CHECK-64-O0-NEXT: blr 1092; 1093; CHECK-32-OPT-LABEL: shuffle_vector_byte_22_14: 1094; CHECK-32-OPT: # %bb.0: # %entry 1095; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 7 1096; CHECK-32-OPT-NEXT: vinsertb 3, 2, 6 1097; CHECK-32-OPT-NEXT: vmr 2, 3 1098; CHECK-32-OPT-NEXT: blr 1099; 1100; CHECK-32-O0-LABEL: shuffle_vector_byte_22_14: 1101; CHECK-32-O0: # %bb.0: # %entry 1102; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 1103; CHECK-32-O0-NEXT: vmr 3, 2 1104; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 1105; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 7 1106; CHECK-32-O0-NEXT: vinsertb 2, 3, 6 1107; CHECK-32-O0-NEXT: blr 1108entry: 1109 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 14, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> 1110 ret <16 x i8> %vecins 1111} 1112 1113define <16 x i8> @shuffle_vector_byte_23_7(<16 x i8> %a, <16 x i8> %b) { 1114; CHECK-64-OPT-LABEL: shuffle_vector_byte_23_7: 1115; CHECK-64-OPT: # %bb.0: # %entry 1116; CHECK-64-OPT-NEXT: vinsertb 3, 2, 7 1117; CHECK-64-OPT-NEXT: vmr 2, 3 1118; CHECK-64-OPT-NEXT: blr 1119; 1120; CHECK-64-O0-LABEL: shuffle_vector_byte_23_7: 1121; CHECK-64-O0: # %bb.0: # %entry 1122; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 1123; CHECK-64-O0-NEXT: vmr 3, 2 1124; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 1125; CHECK-64-O0-NEXT: vinsertb 2, 3, 7 1126; CHECK-64-O0-NEXT: blr 1127; 1128; CHECK-32-OPT-LABEL: shuffle_vector_byte_23_7: 1129; CHECK-32-OPT: # %bb.0: # %entry 1130; CHECK-32-OPT-NEXT: vinsertb 3, 2, 7 1131; CHECK-32-OPT-NEXT: vmr 2, 3 1132; CHECK-32-OPT-NEXT: blr 1133; 1134; CHECK-32-O0-LABEL: shuffle_vector_byte_23_7: 1135; CHECK-32-O0: # %bb.0: # %entry 1136; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 1137; CHECK-32-O0-NEXT: vmr 3, 2 1138; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 1139; CHECK-32-O0-NEXT: vinsertb 2, 3, 7 1140; CHECK-32-O0-NEXT: blr 1141entry: 1142 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 7, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> 1143 ret <16 x i8> %vecins 1144} 1145 1146define <16 x i8> @shuffle_vector_byte_24_0(<16 x i8> %a, <16 x i8> %b) { 1147; CHECK-64-OPT-LABEL: shuffle_vector_byte_24_0: 1148; CHECK-64-OPT: # %bb.0: # %entry 1149; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 9 1150; CHECK-64-OPT-NEXT: vinsertb 3, 2, 8 1151; CHECK-64-OPT-NEXT: vmr 2, 3 1152; CHECK-64-OPT-NEXT: blr 1153; 1154; CHECK-64-O0-LABEL: shuffle_vector_byte_24_0: 1155; CHECK-64-O0: # %bb.0: # %entry 1156; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 1157; CHECK-64-O0-NEXT: vmr 3, 2 1158; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 1159; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 9 1160; CHECK-64-O0-NEXT: vinsertb 2, 3, 8 1161; CHECK-64-O0-NEXT: blr 1162; 1163; CHECK-32-OPT-LABEL: shuffle_vector_byte_24_0: 1164; CHECK-32-OPT: # %bb.0: # %entry 1165; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 9 1166; CHECK-32-OPT-NEXT: vinsertb 3, 2, 8 1167; CHECK-32-OPT-NEXT: vmr 2, 3 1168; CHECK-32-OPT-NEXT: blr 1169; 1170; CHECK-32-O0-LABEL: shuffle_vector_byte_24_0: 1171; CHECK-32-O0: # %bb.0: # %entry 1172; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 1173; CHECK-32-O0-NEXT: vmr 3, 2 1174; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 1175; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 9 1176; CHECK-32-O0-NEXT: vinsertb 2, 3, 8 1177; CHECK-32-O0-NEXT: blr 1178entry: 1179 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 0, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> 1180 ret <16 x i8> %vecins 1181} 1182 1183define <16 x i8> @shuffle_vector_byte_25_9(<16 x i8> %a, <16 x i8> %b) { 1184; CHECK-64-OPT-LABEL: shuffle_vector_byte_25_9: 1185; CHECK-64-OPT: # %bb.0: # %entry 1186; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 2 1187; CHECK-64-OPT-NEXT: vinsertb 3, 2, 9 1188; CHECK-64-OPT-NEXT: vmr 2, 3 1189; CHECK-64-OPT-NEXT: blr 1190; 1191; CHECK-64-O0-LABEL: shuffle_vector_byte_25_9: 1192; CHECK-64-O0: # %bb.0: # %entry 1193; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 1194; CHECK-64-O0-NEXT: vmr 3, 2 1195; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 1196; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 2 1197; CHECK-64-O0-NEXT: vinsertb 2, 3, 9 1198; CHECK-64-O0-NEXT: blr 1199; 1200; CHECK-32-OPT-LABEL: shuffle_vector_byte_25_9: 1201; CHECK-32-OPT: # %bb.0: # %entry 1202; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 2 1203; CHECK-32-OPT-NEXT: vinsertb 3, 2, 9 1204; CHECK-32-OPT-NEXT: vmr 2, 3 1205; CHECK-32-OPT-NEXT: blr 1206; 1207; CHECK-32-O0-LABEL: shuffle_vector_byte_25_9: 1208; CHECK-32-O0: # %bb.0: # %entry 1209; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 1210; CHECK-32-O0-NEXT: vmr 3, 2 1211; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 1212; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 2 1213; CHECK-32-O0-NEXT: vinsertb 2, 3, 9 1214; CHECK-32-O0-NEXT: blr 1215entry: 1216 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 9, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> 1217 ret <16 x i8> %vecins 1218} 1219 1220define <16 x i8> @shuffle_vector_byte_26_2(<16 x i8> %a, <16 x i8> %b) { 1221; CHECK-64-OPT-LABEL: shuffle_vector_byte_26_2: 1222; CHECK-64-OPT: # %bb.0: # %entry 1223; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 11 1224; CHECK-64-OPT-NEXT: vinsertb 3, 2, 10 1225; CHECK-64-OPT-NEXT: vmr 2, 3 1226; CHECK-64-OPT-NEXT: blr 1227; 1228; CHECK-64-O0-LABEL: shuffle_vector_byte_26_2: 1229; CHECK-64-O0: # %bb.0: # %entry 1230; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 1231; CHECK-64-O0-NEXT: vmr 3, 2 1232; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 1233; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 11 1234; CHECK-64-O0-NEXT: vinsertb 2, 3, 10 1235; CHECK-64-O0-NEXT: blr 1236; 1237; CHECK-32-OPT-LABEL: shuffle_vector_byte_26_2: 1238; CHECK-32-OPT: # %bb.0: # %entry 1239; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 11 1240; CHECK-32-OPT-NEXT: vinsertb 3, 2, 10 1241; CHECK-32-OPT-NEXT: vmr 2, 3 1242; CHECK-32-OPT-NEXT: blr 1243; 1244; CHECK-32-O0-LABEL: shuffle_vector_byte_26_2: 1245; CHECK-32-O0: # %bb.0: # %entry 1246; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 1247; CHECK-32-O0-NEXT: vmr 3, 2 1248; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 1249; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 11 1250; CHECK-32-O0-NEXT: vinsertb 2, 3, 10 1251; CHECK-32-O0-NEXT: blr 1252entry: 1253 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 2, i32 27, i32 28, i32 29, i32 30, i32 31> 1254 ret <16 x i8> %vecins 1255} 1256 1257define <16 x i8> @shuffle_vector_byte_27_11(<16 x i8> %a, <16 x i8> %b) { 1258; CHECK-64-OPT-LABEL: shuffle_vector_byte_27_11: 1259; CHECK-64-OPT: # %bb.0: # %entry 1260; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 4 1261; CHECK-64-OPT-NEXT: vinsertb 3, 2, 11 1262; CHECK-64-OPT-NEXT: vmr 2, 3 1263; CHECK-64-OPT-NEXT: blr 1264; 1265; CHECK-64-O0-LABEL: shuffle_vector_byte_27_11: 1266; CHECK-64-O0: # %bb.0: # %entry 1267; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 1268; CHECK-64-O0-NEXT: vmr 3, 2 1269; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 1270; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 4 1271; CHECK-64-O0-NEXT: vinsertb 2, 3, 11 1272; CHECK-64-O0-NEXT: blr 1273; 1274; CHECK-32-OPT-LABEL: shuffle_vector_byte_27_11: 1275; CHECK-32-OPT: # %bb.0: # %entry 1276; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 4 1277; CHECK-32-OPT-NEXT: vinsertb 3, 2, 11 1278; CHECK-32-OPT-NEXT: vmr 2, 3 1279; CHECK-32-OPT-NEXT: blr 1280; 1281; CHECK-32-O0-LABEL: shuffle_vector_byte_27_11: 1282; CHECK-32-O0: # %bb.0: # %entry 1283; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 1284; CHECK-32-O0-NEXT: vmr 3, 2 1285; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 1286; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 4 1287; CHECK-32-O0-NEXT: vinsertb 2, 3, 11 1288; CHECK-32-O0-NEXT: blr 1289entry: 1290 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 11, i32 28, i32 29, i32 30, i32 31> 1291 ret <16 x i8> %vecins 1292} 1293 1294define <16 x i8> @shuffle_vector_byte_28_4(<16 x i8> %a, <16 x i8> %b) { 1295; CHECK-64-OPT-LABEL: shuffle_vector_byte_28_4: 1296; CHECK-64-OPT: # %bb.0: # %entry 1297; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 13 1298; CHECK-64-OPT-NEXT: vinsertb 3, 2, 12 1299; CHECK-64-OPT-NEXT: vmr 2, 3 1300; CHECK-64-OPT-NEXT: blr 1301; 1302; CHECK-64-O0-LABEL: shuffle_vector_byte_28_4: 1303; CHECK-64-O0: # %bb.0: # %entry 1304; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 1305; CHECK-64-O0-NEXT: vmr 3, 2 1306; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 1307; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 13 1308; CHECK-64-O0-NEXT: vinsertb 2, 3, 12 1309; CHECK-64-O0-NEXT: blr 1310; 1311; CHECK-32-OPT-LABEL: shuffle_vector_byte_28_4: 1312; CHECK-32-OPT: # %bb.0: # %entry 1313; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 13 1314; CHECK-32-OPT-NEXT: vinsertb 3, 2, 12 1315; CHECK-32-OPT-NEXT: vmr 2, 3 1316; CHECK-32-OPT-NEXT: blr 1317; 1318; CHECK-32-O0-LABEL: shuffle_vector_byte_28_4: 1319; CHECK-32-O0: # %bb.0: # %entry 1320; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 1321; CHECK-32-O0-NEXT: vmr 3, 2 1322; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 1323; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 13 1324; CHECK-32-O0-NEXT: vinsertb 2, 3, 12 1325; CHECK-32-O0-NEXT: blr 1326entry: 1327 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 4, i32 29, i32 30, i32 31> 1328 ret <16 x i8> %vecins 1329} 1330 1331define <16 x i8> @shuffle_vector_byte_29_13(<16 x i8> %a, <16 x i8> %b) { 1332; CHECK-64-OPT-LABEL: shuffle_vector_byte_29_13: 1333; CHECK-64-OPT: # %bb.0: # %entry 1334; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 6 1335; CHECK-64-OPT-NEXT: vinsertb 3, 2, 13 1336; CHECK-64-OPT-NEXT: vmr 2, 3 1337; CHECK-64-OPT-NEXT: blr 1338; 1339; CHECK-64-O0-LABEL: shuffle_vector_byte_29_13: 1340; CHECK-64-O0: # %bb.0: # %entry 1341; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 1342; CHECK-64-O0-NEXT: vmr 3, 2 1343; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 1344; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 6 1345; CHECK-64-O0-NEXT: vinsertb 2, 3, 13 1346; CHECK-64-O0-NEXT: blr 1347; 1348; CHECK-32-OPT-LABEL: shuffle_vector_byte_29_13: 1349; CHECK-32-OPT: # %bb.0: # %entry 1350; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 6 1351; CHECK-32-OPT-NEXT: vinsertb 3, 2, 13 1352; CHECK-32-OPT-NEXT: vmr 2, 3 1353; CHECK-32-OPT-NEXT: blr 1354; 1355; CHECK-32-O0-LABEL: shuffle_vector_byte_29_13: 1356; CHECK-32-O0: # %bb.0: # %entry 1357; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 1358; CHECK-32-O0-NEXT: vmr 3, 2 1359; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 1360; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 6 1361; CHECK-32-O0-NEXT: vinsertb 2, 3, 13 1362; CHECK-32-O0-NEXT: blr 1363entry: 1364 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 13, i32 30, i32 31> 1365 ret <16 x i8> %vecins 1366} 1367 1368define <16 x i8> @shuffle_vector_byte_30_6(<16 x i8> %a, <16 x i8> %b) { 1369; CHECK-64-OPT-LABEL: shuffle_vector_byte_30_6: 1370; CHECK-64-OPT: # %bb.0: # %entry 1371; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 15 1372; CHECK-64-OPT-NEXT: vinsertb 3, 2, 14 1373; CHECK-64-OPT-NEXT: vmr 2, 3 1374; CHECK-64-OPT-NEXT: blr 1375; 1376; CHECK-64-O0-LABEL: shuffle_vector_byte_30_6: 1377; CHECK-64-O0: # %bb.0: # %entry 1378; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 1379; CHECK-64-O0-NEXT: vmr 3, 2 1380; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 1381; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 15 1382; CHECK-64-O0-NEXT: vinsertb 2, 3, 14 1383; CHECK-64-O0-NEXT: blr 1384; 1385; CHECK-32-OPT-LABEL: shuffle_vector_byte_30_6: 1386; CHECK-32-OPT: # %bb.0: # %entry 1387; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 15 1388; CHECK-32-OPT-NEXT: vinsertb 3, 2, 14 1389; CHECK-32-OPT-NEXT: vmr 2, 3 1390; CHECK-32-OPT-NEXT: blr 1391; 1392; CHECK-32-O0-LABEL: shuffle_vector_byte_30_6: 1393; CHECK-32-O0: # %bb.0: # %entry 1394; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 1395; CHECK-32-O0-NEXT: vmr 3, 2 1396; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 1397; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 15 1398; CHECK-32-O0-NEXT: vinsertb 2, 3, 14 1399; CHECK-32-O0-NEXT: blr 1400entry: 1401 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 6, i32 31> 1402 ret <16 x i8> %vecins 1403} 1404 1405define <16 x i8> @shuffle_vector_byte_31_15(<16 x i8> %a, <16 x i8> %b) { 1406; CHECK-64-OPT-LABEL: shuffle_vector_byte_31_15: 1407; CHECK-64-OPT: # %bb.0: # %entry 1408; CHECK-64-OPT-NEXT: vsldoi 2, 2, 2, 8 1409; CHECK-64-OPT-NEXT: vinsertb 3, 2, 15 1410; CHECK-64-OPT-NEXT: vmr 2, 3 1411; CHECK-64-OPT-NEXT: blr 1412; 1413; CHECK-64-O0-LABEL: shuffle_vector_byte_31_15: 1414; CHECK-64-O0: # %bb.0: # %entry 1415; CHECK-64-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 1416; CHECK-64-O0-NEXT: vmr 3, 2 1417; CHECK-64-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 1418; CHECK-64-O0-NEXT: vsldoi 3, 3, 3, 8 1419; CHECK-64-O0-NEXT: vinsertb 2, 3, 15 1420; CHECK-64-O0-NEXT: blr 1421; 1422; CHECK-32-OPT-LABEL: shuffle_vector_byte_31_15: 1423; CHECK-32-OPT: # %bb.0: # %entry 1424; CHECK-32-OPT-NEXT: vsldoi 2, 2, 2, 8 1425; CHECK-32-OPT-NEXT: vinsertb 3, 2, 15 1426; CHECK-32-OPT-NEXT: vmr 2, 3 1427; CHECK-32-OPT-NEXT: blr 1428; 1429; CHECK-32-O0-LABEL: shuffle_vector_byte_31_15: 1430; CHECK-32-O0: # %bb.0: # %entry 1431; CHECK-32-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill 1432; CHECK-32-O0-NEXT: vmr 3, 2 1433; CHECK-32-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload 1434; CHECK-32-O0-NEXT: vsldoi 3, 3, 3, 8 1435; CHECK-32-O0-NEXT: vinsertb 2, 3, 15 1436; CHECK-32-O0-NEXT: blr 1437entry: 1438 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 15> 1439 ret <16 x i8> %vecins 1440} 1441 1442; The following testcases use the same vector in both arguments of the 1443; shufflevector. If byte element 7 in BE mode(or 8 in LE mode) is the one 1444; we're attempting to insert, then we can use the vector insert instruction 1445define <16 x i8> @shuffle_vector_byte_0_7(<16 x i8> %a) { 1446; CHECK-64-LABEL: shuffle_vector_byte_0_7: 1447; CHECK-64: # %bb.0: # %entry 1448; CHECK-64-NEXT: vinsertb 2, 2, 0 1449; CHECK-64-NEXT: blr 1450; 1451; CHECK-32-LABEL: shuffle_vector_byte_0_7: 1452; CHECK-32: # %bb.0: # %entry 1453; CHECK-32-NEXT: vinsertb 2, 2, 0 1454; CHECK-32-NEXT: blr 1455entry: 1456 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 7, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 1457 ret <16 x i8> %vecins 1458} 1459 1460define <16 x i8> @shuffle_vector_byte_1_8(<16 x i8> %a) { 1461; CHECK-64-LABEL: shuffle_vector_byte_1_8: 1462; CHECK-64: # %bb.0: # %entry 1463; CHECK-64-NEXT: ld 3, L..C4(2) # %const.0 1464; CHECK-64-NEXT: lxv 0, 0(3) 1465; CHECK-64-NEXT: xxperm 34, 34, 0 1466; CHECK-64-NEXT: blr 1467; 1468; CHECK-32-LABEL: shuffle_vector_byte_1_8: 1469; CHECK-32: # %bb.0: # %entry 1470; CHECK-32-NEXT: lwz 3, L..C4(2) # %const.0 1471; CHECK-32-NEXT: lxv 0, 0(3) 1472; CHECK-32-NEXT: xxperm 34, 34, 0 1473; CHECK-32-NEXT: blr 1474entry: 1475 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 8, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 1476 ret <16 x i8> %vecins 1477} 1478 1479define <16 x i8> @shuffle_vector_byte_2_8(<16 x i8> %a) { 1480; CHECK-64-LABEL: shuffle_vector_byte_2_8: 1481; CHECK-64: # %bb.0: # %entry 1482; CHECK-64-NEXT: ld 3, L..C5(2) # %const.0 1483; CHECK-64-NEXT: lxv 0, 0(3) 1484; CHECK-64-NEXT: xxperm 34, 34, 0 1485; CHECK-64-NEXT: blr 1486; 1487; CHECK-32-LABEL: shuffle_vector_byte_2_8: 1488; CHECK-32: # %bb.0: # %entry 1489; CHECK-32-NEXT: lwz 3, L..C5(2) # %const.0 1490; CHECK-32-NEXT: lxv 0, 0(3) 1491; CHECK-32-NEXT: xxperm 34, 34, 0 1492; CHECK-32-NEXT: blr 1493entry: 1494 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 8, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 1495 ret <16 x i8> %vecins 1496} 1497 1498define <16 x i8> @shuffle_vector_byte_3_7(<16 x i8> %a) { 1499; CHECK-64-LABEL: shuffle_vector_byte_3_7: 1500; CHECK-64: # %bb.0: # %entry 1501; CHECK-64-NEXT: vinsertb 2, 2, 3 1502; CHECK-64-NEXT: blr 1503; 1504; CHECK-32-LABEL: shuffle_vector_byte_3_7: 1505; CHECK-32: # %bb.0: # %entry 1506; CHECK-32-NEXT: vinsertb 2, 2, 3 1507; CHECK-32-NEXT: blr 1508entry: 1509 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 7, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 1510 ret <16 x i8> %vecins 1511} 1512 1513define <16 x i8> @shuffle_vector_byte_4_7(<16 x i8> %a) { 1514; CHECK-64-LABEL: shuffle_vector_byte_4_7: 1515; CHECK-64: # %bb.0: # %entry 1516; CHECK-64-NEXT: vinsertb 2, 2, 4 1517; CHECK-64-NEXT: blr 1518; 1519; CHECK-32-LABEL: shuffle_vector_byte_4_7: 1520; CHECK-32: # %bb.0: # %entry 1521; CHECK-32-NEXT: vinsertb 2, 2, 4 1522; CHECK-32-NEXT: blr 1523entry: 1524 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 7, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 1525 ret <16 x i8> %vecins 1526} 1527 1528define <16 x i8> @shuffle_vector_byte_5_8(<16 x i8> %a) { 1529; CHECK-64-LABEL: shuffle_vector_byte_5_8: 1530; CHECK-64: # %bb.0: # %entry 1531; CHECK-64-NEXT: ld 3, L..C6(2) # %const.0 1532; CHECK-64-NEXT: lxv 0, 0(3) 1533; CHECK-64-NEXT: xxperm 34, 34, 0 1534; CHECK-64-NEXT: blr 1535; 1536; CHECK-32-LABEL: shuffle_vector_byte_5_8: 1537; CHECK-32: # %bb.0: # %entry 1538; CHECK-32-NEXT: lwz 3, L..C6(2) # %const.0 1539; CHECK-32-NEXT: lxv 0, 0(3) 1540; CHECK-32-NEXT: xxperm 34, 34, 0 1541; CHECK-32-NEXT: blr 1542entry: 1543 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 8, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 1544 ret <16 x i8> %vecins 1545} 1546 1547define <16 x i8> @shuffle_vector_byte_6_8(<16 x i8> %a) { 1548; CHECK-64-LABEL: shuffle_vector_byte_6_8: 1549; CHECK-64: # %bb.0: # %entry 1550; CHECK-64-NEXT: ld 3, L..C7(2) # %const.0 1551; CHECK-64-NEXT: lxv 0, 0(3) 1552; CHECK-64-NEXT: xxperm 34, 34, 0 1553; CHECK-64-NEXT: blr 1554; 1555; CHECK-32-LABEL: shuffle_vector_byte_6_8: 1556; CHECK-32: # %bb.0: # %entry 1557; CHECK-32-NEXT: lwz 3, L..C7(2) # %const.0 1558; CHECK-32-NEXT: lxv 0, 0(3) 1559; CHECK-32-NEXT: xxperm 34, 34, 0 1560; CHECK-32-NEXT: blr 1561entry: 1562 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 1563 ret <16 x i8> %vecins 1564} 1565 1566define <16 x i8> @shuffle_vector_byte_7_8(<16 x i8> %a) { 1567; CHECK-64-LABEL: shuffle_vector_byte_7_8: 1568; CHECK-64: # %bb.0: # %entry 1569; CHECK-64-NEXT: ld 3, L..C8(2) # %const.0 1570; CHECK-64-NEXT: lxv 0, 0(3) 1571; CHECK-64-NEXT: xxperm 34, 34, 0 1572; CHECK-64-NEXT: blr 1573; 1574; CHECK-32-LABEL: shuffle_vector_byte_7_8: 1575; CHECK-32: # %bb.0: # %entry 1576; CHECK-32-NEXT: lwz 3, L..C8(2) # %const.0 1577; CHECK-32-NEXT: lxv 0, 0(3) 1578; CHECK-32-NEXT: xxperm 34, 34, 0 1579; CHECK-32-NEXT: blr 1580entry: 1581 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 8, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 1582 ret <16 x i8> %vecins 1583} 1584 1585define <16 x i8> @shuffle_vector_byte_8_7(<16 x i8> %a) { 1586; CHECK-64-LABEL: shuffle_vector_byte_8_7: 1587; CHECK-64: # %bb.0: # %entry 1588; CHECK-64-NEXT: vinsertb 2, 2, 8 1589; CHECK-64-NEXT: blr 1590; 1591; CHECK-32-LABEL: shuffle_vector_byte_8_7: 1592; CHECK-32: # %bb.0: # %entry 1593; CHECK-32-NEXT: vinsertb 2, 2, 8 1594; CHECK-32-NEXT: blr 1595entry: 1596 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 7, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 1597 ret <16 x i8> %vecins 1598} 1599 1600define <16 x i8> @shuffle_vector_byte_9_7(<16 x i8> %a) { 1601; CHECK-64-LABEL: shuffle_vector_byte_9_7: 1602; CHECK-64: # %bb.0: # %entry 1603; CHECK-64-NEXT: vinsertb 2, 2, 9 1604; CHECK-64-NEXT: blr 1605; 1606; CHECK-32-LABEL: shuffle_vector_byte_9_7: 1607; CHECK-32: # %bb.0: # %entry 1608; CHECK-32-NEXT: vinsertb 2, 2, 9 1609; CHECK-32-NEXT: blr 1610entry: 1611 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 7, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 1612 ret <16 x i8> %vecins 1613} 1614 1615define <16 x i8> @shuffle_vector_byte_10_7(<16 x i8> %a) { 1616; CHECK-64-LABEL: shuffle_vector_byte_10_7: 1617; CHECK-64: # %bb.0: # %entry 1618; CHECK-64-NEXT: vinsertb 2, 2, 10 1619; CHECK-64-NEXT: blr 1620; 1621; CHECK-32-LABEL: shuffle_vector_byte_10_7: 1622; CHECK-32: # %bb.0: # %entry 1623; CHECK-32-NEXT: vinsertb 2, 2, 10 1624; CHECK-32-NEXT: blr 1625entry: 1626 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 7, i32 11, i32 12, i32 13, i32 14, i32 15> 1627 ret <16 x i8> %vecins 1628} 1629 1630define <16 x i8> @shuffle_vector_byte_11_8(<16 x i8> %a) { 1631; CHECK-64-LABEL: shuffle_vector_byte_11_8: 1632; CHECK-64: # %bb.0: # %entry 1633; CHECK-64-NEXT: ld 3, L..C9(2) # %const.0 1634; CHECK-64-NEXT: lxv 0, 0(3) 1635; CHECK-64-NEXT: xxperm 34, 34, 0 1636; CHECK-64-NEXT: blr 1637; 1638; CHECK-32-LABEL: shuffle_vector_byte_11_8: 1639; CHECK-32: # %bb.0: # %entry 1640; CHECK-32-NEXT: lwz 3, L..C9(2) # %const.0 1641; CHECK-32-NEXT: lxv 0, 0(3) 1642; CHECK-32-NEXT: xxperm 34, 34, 0 1643; CHECK-32-NEXT: blr 1644entry: 1645 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 8, i32 12, i32 13, i32 14, i32 15> 1646 ret <16 x i8> %vecins 1647} 1648 1649define <16 x i8> @shuffle_vector_byte_12_8(<16 x i8> %a) { 1650; CHECK-64-LABEL: shuffle_vector_byte_12_8: 1651; CHECK-64: # %bb.0: # %entry 1652; CHECK-64-NEXT: ld 3, L..C10(2) # %const.0 1653; CHECK-64-NEXT: lxv 0, 0(3) 1654; CHECK-64-NEXT: xxperm 34, 34, 0 1655; CHECK-64-NEXT: blr 1656; 1657; CHECK-32-LABEL: shuffle_vector_byte_12_8: 1658; CHECK-32: # %bb.0: # %entry 1659; CHECK-32-NEXT: lwz 3, L..C10(2) # %const.0 1660; CHECK-32-NEXT: lxv 0, 0(3) 1661; CHECK-32-NEXT: xxperm 34, 34, 0 1662; CHECK-32-NEXT: blr 1663entry: 1664 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 8, i32 13, i32 14, i32 15> 1665 ret <16 x i8> %vecins 1666} 1667 1668define <16 x i8> @shuffle_vector_byte_13_7(<16 x i8> %a) { 1669; CHECK-64-LABEL: shuffle_vector_byte_13_7: 1670; CHECK-64: # %bb.0: # %entry 1671; CHECK-64-NEXT: vinsertb 2, 2, 13 1672; CHECK-64-NEXT: blr 1673; 1674; CHECK-32-LABEL: shuffle_vector_byte_13_7: 1675; CHECK-32: # %bb.0: # %entry 1676; CHECK-32-NEXT: vinsertb 2, 2, 13 1677; CHECK-32-NEXT: blr 1678entry: 1679 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 7, i32 14, i32 15> 1680 ret <16 x i8> %vecins 1681} 1682 1683define <16 x i8> @shuffle_vector_byte_14_7(<16 x i8> %a) { 1684; CHECK-64-LABEL: shuffle_vector_byte_14_7: 1685; CHECK-64: # %bb.0: # %entry 1686; CHECK-64-NEXT: vinsertb 2, 2, 14 1687; CHECK-64-NEXT: blr 1688; 1689; CHECK-32-LABEL: shuffle_vector_byte_14_7: 1690; CHECK-32: # %bb.0: # %entry 1691; CHECK-32-NEXT: vinsertb 2, 2, 14 1692; CHECK-32-NEXT: blr 1693entry: 1694 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 7, i32 15> 1695 ret <16 x i8> %vecins 1696} 1697 1698define <16 x i8> @shuffle_vector_byte_15_8(<16 x i8> %a) { 1699; CHECK-64-LABEL: shuffle_vector_byte_15_8: 1700; CHECK-64: # %bb.0: # %entry 1701; CHECK-64-NEXT: ld 3, L..C11(2) # %const.0 1702; CHECK-64-NEXT: lxv 0, 0(3) 1703; CHECK-64-NEXT: xxperm 34, 34, 0 1704; CHECK-64-NEXT: blr 1705; 1706; CHECK-32-LABEL: shuffle_vector_byte_15_8: 1707; CHECK-32: # %bb.0: # %entry 1708; CHECK-32-NEXT: lwz 3, L..C11(2) # %const.0 1709; CHECK-32-NEXT: lxv 0, 0(3) 1710; CHECK-32-NEXT: xxperm 34, 34, 0 1711; CHECK-32-NEXT: blr 1712entry: 1713 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 8> 1714 ret <16 x i8> %vecins 1715} 1716 1717; The following tests try to insert one halfword element into the vector. We 1718; should always be using the 'vinserth' instruction. 1719define <8 x i16> @insert_halfword_0(<8 x i16> %a, i16 %b) { 1720; CHECK-64-OPT-LABEL: insert_halfword_0: 1721; CHECK-64-OPT: # %bb.0: # %entry 1722; CHECK-64-OPT-NEXT: mtvsrwz 35, 3 1723; CHECK-64-OPT-NEXT: vinserth 2, 3, 0 1724; CHECK-64-OPT-NEXT: blr 1725; 1726; CHECK-64-O0-LABEL: insert_halfword_0: 1727; CHECK-64-O0: # %bb.0: # %entry 1728; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3 1729; CHECK-64-O0-NEXT: mtfprwz 0, 3 1730; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0 1731; CHECK-64-O0-NEXT: vinserth 2, 3, 0 1732; CHECK-64-O0-NEXT: blr 1733; 1734; CHECK-32-OPT-LABEL: insert_halfword_0: 1735; CHECK-32-OPT: # %bb.0: # %entry 1736; CHECK-32-OPT-NEXT: mtvsrwz 35, 3 1737; CHECK-32-OPT-NEXT: vinserth 2, 3, 0 1738; CHECK-32-OPT-NEXT: blr 1739; 1740; CHECK-32-O0-LABEL: insert_halfword_0: 1741; CHECK-32-O0: # %bb.0: # %entry 1742; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3 1743; CHECK-32-O0-NEXT: mtfprwz 0, 3 1744; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0 1745; CHECK-32-O0-NEXT: vinserth 2, 3, 0 1746; CHECK-32-O0-NEXT: blr 1747entry: 1748 %vecins = insertelement <8 x i16> %a, i16 %b, i32 0 1749 ret <8 x i16> %vecins 1750} 1751 1752define <8 x i16> @insert_halfword_1(<8 x i16> %a, i16 %b) { 1753; CHECK-64-OPT-LABEL: insert_halfword_1: 1754; CHECK-64-OPT: # %bb.0: # %entry 1755; CHECK-64-OPT-NEXT: mtvsrwz 35, 3 1756; CHECK-64-OPT-NEXT: vinserth 2, 3, 2 1757; CHECK-64-OPT-NEXT: blr 1758; 1759; CHECK-64-O0-LABEL: insert_halfword_1: 1760; CHECK-64-O0: # %bb.0: # %entry 1761; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3 1762; CHECK-64-O0-NEXT: mtfprwz 0, 3 1763; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0 1764; CHECK-64-O0-NEXT: vinserth 2, 3, 2 1765; CHECK-64-O0-NEXT: blr 1766; 1767; CHECK-32-OPT-LABEL: insert_halfword_1: 1768; CHECK-32-OPT: # %bb.0: # %entry 1769; CHECK-32-OPT-NEXT: mtvsrwz 35, 3 1770; CHECK-32-OPT-NEXT: vinserth 2, 3, 2 1771; CHECK-32-OPT-NEXT: blr 1772; 1773; CHECK-32-O0-LABEL: insert_halfword_1: 1774; CHECK-32-O0: # %bb.0: # %entry 1775; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3 1776; CHECK-32-O0-NEXT: mtfprwz 0, 3 1777; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0 1778; CHECK-32-O0-NEXT: vinserth 2, 3, 2 1779; CHECK-32-O0-NEXT: blr 1780entry: 1781 %vecins = insertelement <8 x i16> %a, i16 %b, i32 1 1782 ret <8 x i16> %vecins 1783} 1784 1785define <8 x i16> @insert_halfword_2(<8 x i16> %a, i16 %b) { 1786; CHECK-64-OPT-LABEL: insert_halfword_2: 1787; CHECK-64-OPT: # %bb.0: # %entry 1788; CHECK-64-OPT-NEXT: mtvsrwz 35, 3 1789; CHECK-64-OPT-NEXT: vinserth 2, 3, 4 1790; CHECK-64-OPT-NEXT: blr 1791; 1792; CHECK-64-O0-LABEL: insert_halfword_2: 1793; CHECK-64-O0: # %bb.0: # %entry 1794; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3 1795; CHECK-64-O0-NEXT: mtfprwz 0, 3 1796; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0 1797; CHECK-64-O0-NEXT: vinserth 2, 3, 4 1798; CHECK-64-O0-NEXT: blr 1799; 1800; CHECK-32-OPT-LABEL: insert_halfword_2: 1801; CHECK-32-OPT: # %bb.0: # %entry 1802; CHECK-32-OPT-NEXT: mtvsrwz 35, 3 1803; CHECK-32-OPT-NEXT: vinserth 2, 3, 4 1804; CHECK-32-OPT-NEXT: blr 1805; 1806; CHECK-32-O0-LABEL: insert_halfword_2: 1807; CHECK-32-O0: # %bb.0: # %entry 1808; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3 1809; CHECK-32-O0-NEXT: mtfprwz 0, 3 1810; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0 1811; CHECK-32-O0-NEXT: vinserth 2, 3, 4 1812; CHECK-32-O0-NEXT: blr 1813entry: 1814 %vecins = insertelement <8 x i16> %a, i16 %b, i32 2 1815 ret <8 x i16> %vecins 1816} 1817 1818define <8 x i16> @insert_halfword_3(<8 x i16> %a, i16 %b) { 1819; CHECK-64-OPT-LABEL: insert_halfword_3: 1820; CHECK-64-OPT: # %bb.0: # %entry 1821; CHECK-64-OPT-NEXT: mtvsrwz 35, 3 1822; CHECK-64-OPT-NEXT: vinserth 2, 3, 6 1823; CHECK-64-OPT-NEXT: blr 1824; 1825; CHECK-64-O0-LABEL: insert_halfword_3: 1826; CHECK-64-O0: # %bb.0: # %entry 1827; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3 1828; CHECK-64-O0-NEXT: mtfprwz 0, 3 1829; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0 1830; CHECK-64-O0-NEXT: vinserth 2, 3, 6 1831; CHECK-64-O0-NEXT: blr 1832; 1833; CHECK-32-OPT-LABEL: insert_halfword_3: 1834; CHECK-32-OPT: # %bb.0: # %entry 1835; CHECK-32-OPT-NEXT: mtvsrwz 35, 3 1836; CHECK-32-OPT-NEXT: vinserth 2, 3, 6 1837; CHECK-32-OPT-NEXT: blr 1838; 1839; CHECK-32-O0-LABEL: insert_halfword_3: 1840; CHECK-32-O0: # %bb.0: # %entry 1841; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3 1842; CHECK-32-O0-NEXT: mtfprwz 0, 3 1843; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0 1844; CHECK-32-O0-NEXT: vinserth 2, 3, 6 1845; CHECK-32-O0-NEXT: blr 1846entry: 1847 %vecins = insertelement <8 x i16> %a, i16 %b, i32 3 1848 ret <8 x i16> %vecins 1849} 1850 1851define <8 x i16> @insert_halfword_4(<8 x i16> %a, i16 %b) { 1852; CHECK-64-OPT-LABEL: insert_halfword_4: 1853; CHECK-64-OPT: # %bb.0: # %entry 1854; CHECK-64-OPT-NEXT: mtvsrwz 35, 3 1855; CHECK-64-OPT-NEXT: vinserth 2, 3, 8 1856; CHECK-64-OPT-NEXT: blr 1857; 1858; CHECK-64-O0-LABEL: insert_halfword_4: 1859; CHECK-64-O0: # %bb.0: # %entry 1860; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3 1861; CHECK-64-O0-NEXT: mtfprwz 0, 3 1862; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0 1863; CHECK-64-O0-NEXT: vinserth 2, 3, 8 1864; CHECK-64-O0-NEXT: blr 1865; 1866; CHECK-32-OPT-LABEL: insert_halfword_4: 1867; CHECK-32-OPT: # %bb.0: # %entry 1868; CHECK-32-OPT-NEXT: mtvsrwz 35, 3 1869; CHECK-32-OPT-NEXT: vinserth 2, 3, 8 1870; CHECK-32-OPT-NEXT: blr 1871; 1872; CHECK-32-O0-LABEL: insert_halfword_4: 1873; CHECK-32-O0: # %bb.0: # %entry 1874; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3 1875; CHECK-32-O0-NEXT: mtfprwz 0, 3 1876; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0 1877; CHECK-32-O0-NEXT: vinserth 2, 3, 8 1878; CHECK-32-O0-NEXT: blr 1879entry: 1880 %vecins = insertelement <8 x i16> %a, i16 %b, i32 4 1881 ret <8 x i16> %vecins 1882} 1883 1884define <8 x i16> @insert_halfword_5(<8 x i16> %a, i16 %b) { 1885; CHECK-64-OPT-LABEL: insert_halfword_5: 1886; CHECK-64-OPT: # %bb.0: # %entry 1887; CHECK-64-OPT-NEXT: mtvsrwz 35, 3 1888; CHECK-64-OPT-NEXT: vinserth 2, 3, 10 1889; CHECK-64-OPT-NEXT: blr 1890; 1891; CHECK-64-O0-LABEL: insert_halfword_5: 1892; CHECK-64-O0: # %bb.0: # %entry 1893; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3 1894; CHECK-64-O0-NEXT: mtfprwz 0, 3 1895; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0 1896; CHECK-64-O0-NEXT: vinserth 2, 3, 10 1897; CHECK-64-O0-NEXT: blr 1898; 1899; CHECK-32-OPT-LABEL: insert_halfword_5: 1900; CHECK-32-OPT: # %bb.0: # %entry 1901; CHECK-32-OPT-NEXT: mtvsrwz 35, 3 1902; CHECK-32-OPT-NEXT: vinserth 2, 3, 10 1903; CHECK-32-OPT-NEXT: blr 1904; 1905; CHECK-32-O0-LABEL: insert_halfword_5: 1906; CHECK-32-O0: # %bb.0: # %entry 1907; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3 1908; CHECK-32-O0-NEXT: mtfprwz 0, 3 1909; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0 1910; CHECK-32-O0-NEXT: vinserth 2, 3, 10 1911; CHECK-32-O0-NEXT: blr 1912entry: 1913 %vecins = insertelement <8 x i16> %a, i16 %b, i32 5 1914 ret <8 x i16> %vecins 1915} 1916 1917define <8 x i16> @insert_halfword_6(<8 x i16> %a, i16 %b) { 1918; CHECK-64-OPT-LABEL: insert_halfword_6: 1919; CHECK-64-OPT: # %bb.0: # %entry 1920; CHECK-64-OPT-NEXT: mtvsrwz 35, 3 1921; CHECK-64-OPT-NEXT: vinserth 2, 3, 12 1922; CHECK-64-OPT-NEXT: blr 1923; 1924; CHECK-64-O0-LABEL: insert_halfword_6: 1925; CHECK-64-O0: # %bb.0: # %entry 1926; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3 1927; CHECK-64-O0-NEXT: mtfprwz 0, 3 1928; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0 1929; CHECK-64-O0-NEXT: vinserth 2, 3, 12 1930; CHECK-64-O0-NEXT: blr 1931; 1932; CHECK-32-OPT-LABEL: insert_halfword_6: 1933; CHECK-32-OPT: # %bb.0: # %entry 1934; CHECK-32-OPT-NEXT: mtvsrwz 35, 3 1935; CHECK-32-OPT-NEXT: vinserth 2, 3, 12 1936; CHECK-32-OPT-NEXT: blr 1937; 1938; CHECK-32-O0-LABEL: insert_halfword_6: 1939; CHECK-32-O0: # %bb.0: # %entry 1940; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3 1941; CHECK-32-O0-NEXT: mtfprwz 0, 3 1942; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0 1943; CHECK-32-O0-NEXT: vinserth 2, 3, 12 1944; CHECK-32-O0-NEXT: blr 1945entry: 1946 %vecins = insertelement <8 x i16> %a, i16 %b, i32 6 1947 ret <8 x i16> %vecins 1948} 1949 1950define <8 x i16> @insert_halfword_7(<8 x i16> %a, i16 %b) { 1951; CHECK-64-OPT-LABEL: insert_halfword_7: 1952; CHECK-64-OPT: # %bb.0: # %entry 1953; CHECK-64-OPT-NEXT: mtvsrwz 35, 3 1954; CHECK-64-OPT-NEXT: vinserth 2, 3, 14 1955; CHECK-64-OPT-NEXT: blr 1956; 1957; CHECK-64-O0-LABEL: insert_halfword_7: 1958; CHECK-64-O0: # %bb.0: # %entry 1959; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3 1960; CHECK-64-O0-NEXT: mtfprwz 0, 3 1961; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0 1962; CHECK-64-O0-NEXT: vinserth 2, 3, 14 1963; CHECK-64-O0-NEXT: blr 1964; 1965; CHECK-32-OPT-LABEL: insert_halfword_7: 1966; CHECK-32-OPT: # %bb.0: # %entry 1967; CHECK-32-OPT-NEXT: mtvsrwz 35, 3 1968; CHECK-32-OPT-NEXT: vinserth 2, 3, 14 1969; CHECK-32-OPT-NEXT: blr 1970; 1971; CHECK-32-O0-LABEL: insert_halfword_7: 1972; CHECK-32-O0: # %bb.0: # %entry 1973; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3 1974; CHECK-32-O0-NEXT: mtfprwz 0, 3 1975; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0 1976; CHECK-32-O0-NEXT: vinserth 2, 3, 14 1977; CHECK-32-O0-NEXT: blr 1978entry: 1979 %vecins = insertelement <8 x i16> %a, i16 %b, i32 7 1980 ret <8 x i16> %vecins 1981} 1982 1983; The following tests try to insert one byte element into the vector. We 1984; should always be using the 'vinsertb' instruction. 1985define <16 x i8> @insert_byte_0(<16 x i8> %a, i8 %b) { 1986; CHECK-64-OPT-LABEL: insert_byte_0: 1987; CHECK-64-OPT: # %bb.0: # %entry 1988; CHECK-64-OPT-NEXT: mtvsrwz 35, 3 1989; CHECK-64-OPT-NEXT: vinsertb 2, 3, 0 1990; CHECK-64-OPT-NEXT: blr 1991; 1992; CHECK-64-O0-LABEL: insert_byte_0: 1993; CHECK-64-O0: # %bb.0: # %entry 1994; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3 1995; CHECK-64-O0-NEXT: mtfprwz 0, 3 1996; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0 1997; CHECK-64-O0-NEXT: vinsertb 2, 3, 0 1998; CHECK-64-O0-NEXT: blr 1999; 2000; CHECK-32-OPT-LABEL: insert_byte_0: 2001; CHECK-32-OPT: # %bb.0: # %entry 2002; CHECK-32-OPT-NEXT: mtvsrwz 35, 3 2003; CHECK-32-OPT-NEXT: vinsertb 2, 3, 0 2004; CHECK-32-OPT-NEXT: blr 2005; 2006; CHECK-32-O0-LABEL: insert_byte_0: 2007; CHECK-32-O0: # %bb.0: # %entry 2008; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3 2009; CHECK-32-O0-NEXT: mtfprwz 0, 3 2010; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0 2011; CHECK-32-O0-NEXT: vinsertb 2, 3, 0 2012; CHECK-32-O0-NEXT: blr 2013entry: 2014 %vecins = insertelement <16 x i8> %a, i8 %b, i32 0 2015 ret <16 x i8> %vecins 2016} 2017 2018define <16 x i8> @insert_byte_1(<16 x i8> %a, i8 %b) { 2019; CHECK-64-OPT-LABEL: insert_byte_1: 2020; CHECK-64-OPT: # %bb.0: # %entry 2021; CHECK-64-OPT-NEXT: mtvsrwz 35, 3 2022; CHECK-64-OPT-NEXT: vinsertb 2, 3, 1 2023; CHECK-64-OPT-NEXT: blr 2024; 2025; CHECK-64-O0-LABEL: insert_byte_1: 2026; CHECK-64-O0: # %bb.0: # %entry 2027; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3 2028; CHECK-64-O0-NEXT: mtfprwz 0, 3 2029; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0 2030; CHECK-64-O0-NEXT: vinsertb 2, 3, 1 2031; CHECK-64-O0-NEXT: blr 2032; 2033; CHECK-32-OPT-LABEL: insert_byte_1: 2034; CHECK-32-OPT: # %bb.0: # %entry 2035; CHECK-32-OPT-NEXT: mtvsrwz 35, 3 2036; CHECK-32-OPT-NEXT: vinsertb 2, 3, 1 2037; CHECK-32-OPT-NEXT: blr 2038; 2039; CHECK-32-O0-LABEL: insert_byte_1: 2040; CHECK-32-O0: # %bb.0: # %entry 2041; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3 2042; CHECK-32-O0-NEXT: mtfprwz 0, 3 2043; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0 2044; CHECK-32-O0-NEXT: vinsertb 2, 3, 1 2045; CHECK-32-O0-NEXT: blr 2046entry: 2047 %vecins = insertelement <16 x i8> %a, i8 %b, i32 1 2048 ret <16 x i8> %vecins 2049} 2050 2051define <16 x i8> @insert_byte_2(<16 x i8> %a, i8 %b) { 2052; CHECK-64-OPT-LABEL: insert_byte_2: 2053; CHECK-64-OPT: # %bb.0: # %entry 2054; CHECK-64-OPT-NEXT: mtvsrwz 35, 3 2055; CHECK-64-OPT-NEXT: vinsertb 2, 3, 2 2056; CHECK-64-OPT-NEXT: blr 2057; 2058; CHECK-64-O0-LABEL: insert_byte_2: 2059; CHECK-64-O0: # %bb.0: # %entry 2060; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3 2061; CHECK-64-O0-NEXT: mtfprwz 0, 3 2062; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0 2063; CHECK-64-O0-NEXT: vinsertb 2, 3, 2 2064; CHECK-64-O0-NEXT: blr 2065; 2066; CHECK-32-OPT-LABEL: insert_byte_2: 2067; CHECK-32-OPT: # %bb.0: # %entry 2068; CHECK-32-OPT-NEXT: mtvsrwz 35, 3 2069; CHECK-32-OPT-NEXT: vinsertb 2, 3, 2 2070; CHECK-32-OPT-NEXT: blr 2071; 2072; CHECK-32-O0-LABEL: insert_byte_2: 2073; CHECK-32-O0: # %bb.0: # %entry 2074; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3 2075; CHECK-32-O0-NEXT: mtfprwz 0, 3 2076; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0 2077; CHECK-32-O0-NEXT: vinsertb 2, 3, 2 2078; CHECK-32-O0-NEXT: blr 2079entry: 2080 %vecins = insertelement <16 x i8> %a, i8 %b, i32 2 2081 ret <16 x i8> %vecins 2082} 2083 2084define <16 x i8> @insert_byte_3(<16 x i8> %a, i8 %b) { 2085; CHECK-64-OPT-LABEL: insert_byte_3: 2086; CHECK-64-OPT: # %bb.0: # %entry 2087; CHECK-64-OPT-NEXT: mtvsrwz 35, 3 2088; CHECK-64-OPT-NEXT: vinsertb 2, 3, 3 2089; CHECK-64-OPT-NEXT: blr 2090; 2091; CHECK-64-O0-LABEL: insert_byte_3: 2092; CHECK-64-O0: # %bb.0: # %entry 2093; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3 2094; CHECK-64-O0-NEXT: mtfprwz 0, 3 2095; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0 2096; CHECK-64-O0-NEXT: vinsertb 2, 3, 3 2097; CHECK-64-O0-NEXT: blr 2098; 2099; CHECK-32-OPT-LABEL: insert_byte_3: 2100; CHECK-32-OPT: # %bb.0: # %entry 2101; CHECK-32-OPT-NEXT: mtvsrwz 35, 3 2102; CHECK-32-OPT-NEXT: vinsertb 2, 3, 3 2103; CHECK-32-OPT-NEXT: blr 2104; 2105; CHECK-32-O0-LABEL: insert_byte_3: 2106; CHECK-32-O0: # %bb.0: # %entry 2107; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3 2108; CHECK-32-O0-NEXT: mtfprwz 0, 3 2109; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0 2110; CHECK-32-O0-NEXT: vinsertb 2, 3, 3 2111; CHECK-32-O0-NEXT: blr 2112entry: 2113 %vecins = insertelement <16 x i8> %a, i8 %b, i32 3 2114 ret <16 x i8> %vecins 2115} 2116 2117define <16 x i8> @insert_byte_4(<16 x i8> %a, i8 %b) { 2118; CHECK-64-OPT-LABEL: insert_byte_4: 2119; CHECK-64-OPT: # %bb.0: # %entry 2120; CHECK-64-OPT-NEXT: mtvsrwz 35, 3 2121; CHECK-64-OPT-NEXT: vinsertb 2, 3, 4 2122; CHECK-64-OPT-NEXT: blr 2123; 2124; CHECK-64-O0-LABEL: insert_byte_4: 2125; CHECK-64-O0: # %bb.0: # %entry 2126; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3 2127; CHECK-64-O0-NEXT: mtfprwz 0, 3 2128; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0 2129; CHECK-64-O0-NEXT: vinsertb 2, 3, 4 2130; CHECK-64-O0-NEXT: blr 2131; 2132; CHECK-32-OPT-LABEL: insert_byte_4: 2133; CHECK-32-OPT: # %bb.0: # %entry 2134; CHECK-32-OPT-NEXT: mtvsrwz 35, 3 2135; CHECK-32-OPT-NEXT: vinsertb 2, 3, 4 2136; CHECK-32-OPT-NEXT: blr 2137; 2138; CHECK-32-O0-LABEL: insert_byte_4: 2139; CHECK-32-O0: # %bb.0: # %entry 2140; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3 2141; CHECK-32-O0-NEXT: mtfprwz 0, 3 2142; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0 2143; CHECK-32-O0-NEXT: vinsertb 2, 3, 4 2144; CHECK-32-O0-NEXT: blr 2145entry: 2146 %vecins = insertelement <16 x i8> %a, i8 %b, i32 4 2147 ret <16 x i8> %vecins 2148} 2149 2150define <16 x i8> @insert_byte_5(<16 x i8> %a, i8 %b) { 2151; CHECK-64-OPT-LABEL: insert_byte_5: 2152; CHECK-64-OPT: # %bb.0: # %entry 2153; CHECK-64-OPT-NEXT: mtvsrwz 35, 3 2154; CHECK-64-OPT-NEXT: vinsertb 2, 3, 5 2155; CHECK-64-OPT-NEXT: blr 2156; 2157; CHECK-64-O0-LABEL: insert_byte_5: 2158; CHECK-64-O0: # %bb.0: # %entry 2159; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3 2160; CHECK-64-O0-NEXT: mtfprwz 0, 3 2161; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0 2162; CHECK-64-O0-NEXT: vinsertb 2, 3, 5 2163; CHECK-64-O0-NEXT: blr 2164; 2165; CHECK-32-OPT-LABEL: insert_byte_5: 2166; CHECK-32-OPT: # %bb.0: # %entry 2167; CHECK-32-OPT-NEXT: mtvsrwz 35, 3 2168; CHECK-32-OPT-NEXT: vinsertb 2, 3, 5 2169; CHECK-32-OPT-NEXT: blr 2170; 2171; CHECK-32-O0-LABEL: insert_byte_5: 2172; CHECK-32-O0: # %bb.0: # %entry 2173; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3 2174; CHECK-32-O0-NEXT: mtfprwz 0, 3 2175; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0 2176; CHECK-32-O0-NEXT: vinsertb 2, 3, 5 2177; CHECK-32-O0-NEXT: blr 2178entry: 2179 %vecins = insertelement <16 x i8> %a, i8 %b, i32 5 2180 ret <16 x i8> %vecins 2181} 2182 2183define <16 x i8> @insert_byte_6(<16 x i8> %a, i8 %b) { 2184; CHECK-64-OPT-LABEL: insert_byte_6: 2185; CHECK-64-OPT: # %bb.0: # %entry 2186; CHECK-64-OPT-NEXT: mtvsrwz 35, 3 2187; CHECK-64-OPT-NEXT: vinsertb 2, 3, 6 2188; CHECK-64-OPT-NEXT: blr 2189; 2190; CHECK-64-O0-LABEL: insert_byte_6: 2191; CHECK-64-O0: # %bb.0: # %entry 2192; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3 2193; CHECK-64-O0-NEXT: mtfprwz 0, 3 2194; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0 2195; CHECK-64-O0-NEXT: vinsertb 2, 3, 6 2196; CHECK-64-O0-NEXT: blr 2197; 2198; CHECK-32-OPT-LABEL: insert_byte_6: 2199; CHECK-32-OPT: # %bb.0: # %entry 2200; CHECK-32-OPT-NEXT: mtvsrwz 35, 3 2201; CHECK-32-OPT-NEXT: vinsertb 2, 3, 6 2202; CHECK-32-OPT-NEXT: blr 2203; 2204; CHECK-32-O0-LABEL: insert_byte_6: 2205; CHECK-32-O0: # %bb.0: # %entry 2206; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3 2207; CHECK-32-O0-NEXT: mtfprwz 0, 3 2208; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0 2209; CHECK-32-O0-NEXT: vinsertb 2, 3, 6 2210; CHECK-32-O0-NEXT: blr 2211entry: 2212 %vecins = insertelement <16 x i8> %a, i8 %b, i32 6 2213 ret <16 x i8> %vecins 2214} 2215 2216define <16 x i8> @insert_byte_7(<16 x i8> %a, i8 %b) { 2217; CHECK-64-OPT-LABEL: insert_byte_7: 2218; CHECK-64-OPT: # %bb.0: # %entry 2219; CHECK-64-OPT-NEXT: mtvsrwz 35, 3 2220; CHECK-64-OPT-NEXT: vinsertb 2, 3, 7 2221; CHECK-64-OPT-NEXT: blr 2222; 2223; CHECK-64-O0-LABEL: insert_byte_7: 2224; CHECK-64-O0: # %bb.0: # %entry 2225; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3 2226; CHECK-64-O0-NEXT: mtfprwz 0, 3 2227; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0 2228; CHECK-64-O0-NEXT: vinsertb 2, 3, 7 2229; CHECK-64-O0-NEXT: blr 2230; 2231; CHECK-32-OPT-LABEL: insert_byte_7: 2232; CHECK-32-OPT: # %bb.0: # %entry 2233; CHECK-32-OPT-NEXT: mtvsrwz 35, 3 2234; CHECK-32-OPT-NEXT: vinsertb 2, 3, 7 2235; CHECK-32-OPT-NEXT: blr 2236; 2237; CHECK-32-O0-LABEL: insert_byte_7: 2238; CHECK-32-O0: # %bb.0: # %entry 2239; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3 2240; CHECK-32-O0-NEXT: mtfprwz 0, 3 2241; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0 2242; CHECK-32-O0-NEXT: vinsertb 2, 3, 7 2243; CHECK-32-O0-NEXT: blr 2244entry: 2245 %vecins = insertelement <16 x i8> %a, i8 %b, i32 7 2246 ret <16 x i8> %vecins 2247} 2248 2249define <16 x i8> @insert_byte_8(<16 x i8> %a, i8 %b) { 2250; CHECK-64-OPT-LABEL: insert_byte_8: 2251; CHECK-64-OPT: # %bb.0: # %entry 2252; CHECK-64-OPT-NEXT: mtvsrwz 35, 3 2253; CHECK-64-OPT-NEXT: vinsertb 2, 3, 8 2254; CHECK-64-OPT-NEXT: blr 2255; 2256; CHECK-64-O0-LABEL: insert_byte_8: 2257; CHECK-64-O0: # %bb.0: # %entry 2258; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3 2259; CHECK-64-O0-NEXT: mtfprwz 0, 3 2260; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0 2261; CHECK-64-O0-NEXT: vinsertb 2, 3, 8 2262; CHECK-64-O0-NEXT: blr 2263; 2264; CHECK-32-OPT-LABEL: insert_byte_8: 2265; CHECK-32-OPT: # %bb.0: # %entry 2266; CHECK-32-OPT-NEXT: mtvsrwz 35, 3 2267; CHECK-32-OPT-NEXT: vinsertb 2, 3, 8 2268; CHECK-32-OPT-NEXT: blr 2269; 2270; CHECK-32-O0-LABEL: insert_byte_8: 2271; CHECK-32-O0: # %bb.0: # %entry 2272; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3 2273; CHECK-32-O0-NEXT: mtfprwz 0, 3 2274; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0 2275; CHECK-32-O0-NEXT: vinsertb 2, 3, 8 2276; CHECK-32-O0-NEXT: blr 2277entry: 2278 %vecins = insertelement <16 x i8> %a, i8 %b, i32 8 2279 ret <16 x i8> %vecins 2280} 2281 2282define <16 x i8> @insert_byte_9(<16 x i8> %a, i8 %b) { 2283; CHECK-64-OPT-LABEL: insert_byte_9: 2284; CHECK-64-OPT: # %bb.0: # %entry 2285; CHECK-64-OPT-NEXT: mtvsrwz 35, 3 2286; CHECK-64-OPT-NEXT: vinsertb 2, 3, 9 2287; CHECK-64-OPT-NEXT: blr 2288; 2289; CHECK-64-O0-LABEL: insert_byte_9: 2290; CHECK-64-O0: # %bb.0: # %entry 2291; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3 2292; CHECK-64-O0-NEXT: mtfprwz 0, 3 2293; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0 2294; CHECK-64-O0-NEXT: vinsertb 2, 3, 9 2295; CHECK-64-O0-NEXT: blr 2296; 2297; CHECK-32-OPT-LABEL: insert_byte_9: 2298; CHECK-32-OPT: # %bb.0: # %entry 2299; CHECK-32-OPT-NEXT: mtvsrwz 35, 3 2300; CHECK-32-OPT-NEXT: vinsertb 2, 3, 9 2301; CHECK-32-OPT-NEXT: blr 2302; 2303; CHECK-32-O0-LABEL: insert_byte_9: 2304; CHECK-32-O0: # %bb.0: # %entry 2305; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3 2306; CHECK-32-O0-NEXT: mtfprwz 0, 3 2307; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0 2308; CHECK-32-O0-NEXT: vinsertb 2, 3, 9 2309; CHECK-32-O0-NEXT: blr 2310entry: 2311 %vecins = insertelement <16 x i8> %a, i8 %b, i32 9 2312 ret <16 x i8> %vecins 2313} 2314 2315define <16 x i8> @insert_byte_10(<16 x i8> %a, i8 %b) { 2316; CHECK-64-OPT-LABEL: insert_byte_10: 2317; CHECK-64-OPT: # %bb.0: # %entry 2318; CHECK-64-OPT-NEXT: mtvsrwz 35, 3 2319; CHECK-64-OPT-NEXT: vinsertb 2, 3, 10 2320; CHECK-64-OPT-NEXT: blr 2321; 2322; CHECK-64-O0-LABEL: insert_byte_10: 2323; CHECK-64-O0: # %bb.0: # %entry 2324; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3 2325; CHECK-64-O0-NEXT: mtfprwz 0, 3 2326; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0 2327; CHECK-64-O0-NEXT: vinsertb 2, 3, 10 2328; CHECK-64-O0-NEXT: blr 2329; 2330; CHECK-32-OPT-LABEL: insert_byte_10: 2331; CHECK-32-OPT: # %bb.0: # %entry 2332; CHECK-32-OPT-NEXT: mtvsrwz 35, 3 2333; CHECK-32-OPT-NEXT: vinsertb 2, 3, 10 2334; CHECK-32-OPT-NEXT: blr 2335; 2336; CHECK-32-O0-LABEL: insert_byte_10: 2337; CHECK-32-O0: # %bb.0: # %entry 2338; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3 2339; CHECK-32-O0-NEXT: mtfprwz 0, 3 2340; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0 2341; CHECK-32-O0-NEXT: vinsertb 2, 3, 10 2342; CHECK-32-O0-NEXT: blr 2343entry: 2344 %vecins = insertelement <16 x i8> %a, i8 %b, i32 10 2345 ret <16 x i8> %vecins 2346} 2347 2348define <16 x i8> @insert_byte_11(<16 x i8> %a, i8 %b) { 2349; CHECK-64-OPT-LABEL: insert_byte_11: 2350; CHECK-64-OPT: # %bb.0: # %entry 2351; CHECK-64-OPT-NEXT: mtvsrwz 35, 3 2352; CHECK-64-OPT-NEXT: vinsertb 2, 3, 11 2353; CHECK-64-OPT-NEXT: blr 2354; 2355; CHECK-64-O0-LABEL: insert_byte_11: 2356; CHECK-64-O0: # %bb.0: # %entry 2357; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3 2358; CHECK-64-O0-NEXT: mtfprwz 0, 3 2359; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0 2360; CHECK-64-O0-NEXT: vinsertb 2, 3, 11 2361; CHECK-64-O0-NEXT: blr 2362; 2363; CHECK-32-OPT-LABEL: insert_byte_11: 2364; CHECK-32-OPT: # %bb.0: # %entry 2365; CHECK-32-OPT-NEXT: mtvsrwz 35, 3 2366; CHECK-32-OPT-NEXT: vinsertb 2, 3, 11 2367; CHECK-32-OPT-NEXT: blr 2368; 2369; CHECK-32-O0-LABEL: insert_byte_11: 2370; CHECK-32-O0: # %bb.0: # %entry 2371; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3 2372; CHECK-32-O0-NEXT: mtfprwz 0, 3 2373; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0 2374; CHECK-32-O0-NEXT: vinsertb 2, 3, 11 2375; CHECK-32-O0-NEXT: blr 2376entry: 2377 %vecins = insertelement <16 x i8> %a, i8 %b, i32 11 2378 ret <16 x i8> %vecins 2379} 2380 2381define <16 x i8> @insert_byte_12(<16 x i8> %a, i8 %b) { 2382; CHECK-64-OPT-LABEL: insert_byte_12: 2383; CHECK-64-OPT: # %bb.0: # %entry 2384; CHECK-64-OPT-NEXT: mtvsrwz 35, 3 2385; CHECK-64-OPT-NEXT: vinsertb 2, 3, 12 2386; CHECK-64-OPT-NEXT: blr 2387; 2388; CHECK-64-O0-LABEL: insert_byte_12: 2389; CHECK-64-O0: # %bb.0: # %entry 2390; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3 2391; CHECK-64-O0-NEXT: mtfprwz 0, 3 2392; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0 2393; CHECK-64-O0-NEXT: vinsertb 2, 3, 12 2394; CHECK-64-O0-NEXT: blr 2395; 2396; CHECK-32-OPT-LABEL: insert_byte_12: 2397; CHECK-32-OPT: # %bb.0: # %entry 2398; CHECK-32-OPT-NEXT: mtvsrwz 35, 3 2399; CHECK-32-OPT-NEXT: vinsertb 2, 3, 12 2400; CHECK-32-OPT-NEXT: blr 2401; 2402; CHECK-32-O0-LABEL: insert_byte_12: 2403; CHECK-32-O0: # %bb.0: # %entry 2404; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3 2405; CHECK-32-O0-NEXT: mtfprwz 0, 3 2406; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0 2407; CHECK-32-O0-NEXT: vinsertb 2, 3, 12 2408; CHECK-32-O0-NEXT: blr 2409entry: 2410 %vecins = insertelement <16 x i8> %a, i8 %b, i32 12 2411 ret <16 x i8> %vecins 2412} 2413 2414define <16 x i8> @insert_byte_13(<16 x i8> %a, i8 %b) { 2415; CHECK-64-OPT-LABEL: insert_byte_13: 2416; CHECK-64-OPT: # %bb.0: # %entry 2417; CHECK-64-OPT-NEXT: mtvsrwz 35, 3 2418; CHECK-64-OPT-NEXT: vinsertb 2, 3, 13 2419; CHECK-64-OPT-NEXT: blr 2420; 2421; CHECK-64-O0-LABEL: insert_byte_13: 2422; CHECK-64-O0: # %bb.0: # %entry 2423; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3 2424; CHECK-64-O0-NEXT: mtfprwz 0, 3 2425; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0 2426; CHECK-64-O0-NEXT: vinsertb 2, 3, 13 2427; CHECK-64-O0-NEXT: blr 2428; 2429; CHECK-32-OPT-LABEL: insert_byte_13: 2430; CHECK-32-OPT: # %bb.0: # %entry 2431; CHECK-32-OPT-NEXT: mtvsrwz 35, 3 2432; CHECK-32-OPT-NEXT: vinsertb 2, 3, 13 2433; CHECK-32-OPT-NEXT: blr 2434; 2435; CHECK-32-O0-LABEL: insert_byte_13: 2436; CHECK-32-O0: # %bb.0: # %entry 2437; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3 2438; CHECK-32-O0-NEXT: mtfprwz 0, 3 2439; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0 2440; CHECK-32-O0-NEXT: vinsertb 2, 3, 13 2441; CHECK-32-O0-NEXT: blr 2442entry: 2443 %vecins = insertelement <16 x i8> %a, i8 %b, i32 13 2444 ret <16 x i8> %vecins 2445} 2446 2447define <16 x i8> @insert_byte_14(<16 x i8> %a, i8 %b) { 2448; CHECK-64-OPT-LABEL: insert_byte_14: 2449; CHECK-64-OPT: # %bb.0: # %entry 2450; CHECK-64-OPT-NEXT: mtvsrwz 35, 3 2451; CHECK-64-OPT-NEXT: vinsertb 2, 3, 14 2452; CHECK-64-OPT-NEXT: blr 2453; 2454; CHECK-64-O0-LABEL: insert_byte_14: 2455; CHECK-64-O0: # %bb.0: # %entry 2456; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3 2457; CHECK-64-O0-NEXT: mtfprwz 0, 3 2458; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0 2459; CHECK-64-O0-NEXT: vinsertb 2, 3, 14 2460; CHECK-64-O0-NEXT: blr 2461; 2462; CHECK-32-OPT-LABEL: insert_byte_14: 2463; CHECK-32-OPT: # %bb.0: # %entry 2464; CHECK-32-OPT-NEXT: mtvsrwz 35, 3 2465; CHECK-32-OPT-NEXT: vinsertb 2, 3, 14 2466; CHECK-32-OPT-NEXT: blr 2467; 2468; CHECK-32-O0-LABEL: insert_byte_14: 2469; CHECK-32-O0: # %bb.0: # %entry 2470; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3 2471; CHECK-32-O0-NEXT: mtfprwz 0, 3 2472; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0 2473; CHECK-32-O0-NEXT: vinsertb 2, 3, 14 2474; CHECK-32-O0-NEXT: blr 2475entry: 2476 %vecins = insertelement <16 x i8> %a, i8 %b, i32 14 2477 ret <16 x i8> %vecins 2478} 2479 2480define <16 x i8> @insert_byte_15(<16 x i8> %a, i8 %b) { 2481; CHECK-64-OPT-LABEL: insert_byte_15: 2482; CHECK-64-OPT: # %bb.0: # %entry 2483; CHECK-64-OPT-NEXT: mtvsrwz 35, 3 2484; CHECK-64-OPT-NEXT: vinsertb 2, 3, 15 2485; CHECK-64-OPT-NEXT: blr 2486; 2487; CHECK-64-O0-LABEL: insert_byte_15: 2488; CHECK-64-O0: # %bb.0: # %entry 2489; CHECK-64-O0-NEXT: # kill: def $r3 killed $r3 killed $x3 2490; CHECK-64-O0-NEXT: mtfprwz 0, 3 2491; CHECK-64-O0-NEXT: xscpsgndp 35, 0, 0 2492; CHECK-64-O0-NEXT: vinsertb 2, 3, 15 2493; CHECK-64-O0-NEXT: blr 2494; 2495; CHECK-32-OPT-LABEL: insert_byte_15: 2496; CHECK-32-OPT: # %bb.0: # %entry 2497; CHECK-32-OPT-NEXT: mtvsrwz 35, 3 2498; CHECK-32-OPT-NEXT: vinsertb 2, 3, 15 2499; CHECK-32-OPT-NEXT: blr 2500; 2501; CHECK-32-O0-LABEL: insert_byte_15: 2502; CHECK-32-O0: # %bb.0: # %entry 2503; CHECK-32-O0-NEXT: # kill: def $r4 killed $r3 2504; CHECK-32-O0-NEXT: mtfprwz 0, 3 2505; CHECK-32-O0-NEXT: xscpsgndp 35, 0, 0 2506; CHECK-32-O0-NEXT: vinsertb 2, 3, 15 2507; CHECK-32-O0-NEXT: blr 2508entry: 2509 %vecins = insertelement <16 x i8> %a, i8 %b, i32 15 2510 ret <16 x i8> %vecins 2511} 2512