1; RUN: llc -mtriple powerpc-ibm-aix-xcoff -stop-after=machine-cp -mcpu=pwr4 \ 2; RUN: -mattr=-altivec -verify-machineinstrs < %s | \ 3; RUN: FileCheck --check-prefixes=CHECK,32BIT %s 4 5; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \ 6; RUN: -mtriple powerpc-ibm-aix-xcoff < %s | \ 7; RUN: FileCheck --check-prefixes=CHECKASM,ASM32 %s 8 9; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -stop-after=machine-cp -mcpu=pwr4 \ 10; RUN: -mattr=-altivec -verify-machineinstrs < %s | \ 11; RUN: FileCheck --check-prefixes=CHECK,64BIT %s 12 13; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \ 14; RUN: -mtriple powerpc64-ibm-aix-xcoff < %s | \ 15; RUN: FileCheck --check-prefixes=CHECKASM,ASM64 %s 16 17%struct.S0 = type {} 18 19%struct.S1 = type { [1 x i8] } 20@gS1 = external global %struct.S1, align 1 21 22define void @call_test_byval_1Byte() { 23entry: 24 %s0 = alloca %struct.S0, align 8 25 %call = call zeroext i8 @test_byval_1Byte(ptr byval(%struct.S0) align 1 %s0, ptr byval(%struct.S1) align 1 @gS1) 26 ret void 27} 28 29 30; CHECK-LABEL: name: call_test_byval_1Byte{{.*}} 31 32; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 33; 32BIT-NEXT: renamable $r[[REG:[0-9]+]] = LWZtoc @gS1, $r2 :: (load (s32) from got) 34; 32BIT-NEXT: renamable $r3 = LBZ 0, killed renamable $r[[REG]] :: (load (s8)) 35; 32BIT-NEXT: renamable $r3 = RLWINM killed renamable $r3, 24, 0, 7 36; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_1Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r2, implicit-def $r1 37; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 38 39; CHECKASM-LABEL: .call_test_byval_1Byte: 40 41; ASM32: stwu 1, -64(1) 42; ASM32-NEXT: lwz [[REG:[0-9]+]], L..C{{[0-9]+}}(2) 43; ASM32-NEXT: stw 0, 72(1) 44; ASM32-NEXT: lbz 3, 0([[REG]]) 45; ASM32-NEXT: slwi 3, 3, 24 46; ASM32-NEXT: bl .test_byval_1Byte 47; ASM32-NEXT: nop 48; ASM32-NEXT: addi 1, 1, 64 49 50; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 51; 64BIT-NEXT: renamable $x[[REG:[0-9]+]] = LDtoc @gS1, $x2 :: (load (s64) from got) 52; 64BIT-NEXT: renamable $x3 = LBZ8 0, killed renamable $x[[REG]] :: (load (s8)) 53; 64BIT-NEXT: renamable $x3 = RLDICR killed renamable $x3, 56, 7 54; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_1Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1 55; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 56 57; ASM64: stdu 1, -128(1) 58; ASM64-NEXT: ld [[REG:[0-9]+]], L..C{{[0-9]+}}(2) 59; ASM64-NEXT: std 0, 144(1) 60; ASM64-NEXT: lbz 3, 0([[REG]]) 61; ASM64-NEXT: sldi 3, 3, 56 62; ASM64-NEXT: bl .test_byval_1Byte 63; ASM64-NEXT: nop 64; ASM64-NEXT: addi 1, 1, 128 65 66 67define zeroext i8 @test_byval_1Byte(ptr byval(%struct.S0) align 1 %s0, ptr byval(%struct.S1) align 1 %s) { 68entry: 69 %0 = load i8, ptr %s, align 1 70 ret i8 %0 71} 72 73; CHECK-LABEL: name: test_byval_1Byte 74 75; 32BIT: fixedStack: 76; 32BIT-NEXT: - { id: 0, type: default, offset: 24, size: 4, alignment: 8, stack-id: default, 77; 32BIT-NEXT: isImmutable: false, isAliased: true, callee-saved-register: '', callee-saved-restored: true, 78; 32BIT: - { id: 1, type: default, offset: 24, size: 4, alignment: 8, stack-id: default, 79; 32BIT-NEXT: isImmutable: false, isAliased: true, callee-saved-register: '', callee-saved-restored: true, 80 81; 32BIT: bb.0.entry: 82; 32BIT-NEXT: liveins: $r3 83; 32BIT: renamable $r4 = COPY $r3 84; 32BIT: renamable $r3 = RLWINM $r3, 8, 24, 31 85; 32BIT: STW killed renamable $r4, 0, %fixed-stack.0 :: (store (s32) into %fixed-stack.0, align 8) 86; 32BIT-NEXT: BLR 87 88; 64BIT: fixedStack: 89; 64BIT-NEXT: - { id: 0, type: default, offset: 48, size: 8, alignment: 16, stack-id: default, 90; 64BIT-NEXT: isImmutable: false, isAliased: true, callee-saved-register: '', callee-saved-restored: true, 91; 64BIT: - { id: 1, type: default, offset: 48, size: 8, alignment: 16, stack-id: default, 92; 64BIT-NEXT: isImmutable: false, isAliased: true, callee-saved-register: '', callee-saved-restored: true, 93 94; 64BIT: bb.0.entry: 95; 64BIT-NEXT: liveins: $x3 96; 64BIT: renamable $x4 = COPY $x3 97; 64BIT: renamable $x3 = RLDICL $x3, 8, 56 98; 64BIT: STD killed renamable $x4, 0, %fixed-stack.0 :: (store (s64) into %fixed-stack.0, align 16) 99 100; CHECKASM-LABEL: .test_byval_1Byte: 101 102; ASM32: mr 4, 3 103; ASM32-NEXT: srwi 3, 3, 24 104; ASM32-NEXT: stw 4, 24(1) 105; ASM32-NEXT: blr 106 107; ASM64: mr 4, 3 108; ASM64-NEXT: rldicl 3, 3, 8, 56 109; ASM64-NEXT: std 4, 48(1) 110; ASM64-NEXT: blr 111 112 113@f = common global float 0.000000e+00, align 4 114 115%struct.S2 = type { [2 x i8] } 116 117@gS2 = external global %struct.S2, align 1 118 119define void @call_test_byval_2Byte() { 120entry: 121 %0 = load float, ptr @f, align 4 122 %call = call zeroext i8 @test_byval_2Byte(i32 signext 42, float %0, ptr byval(%struct.S2) align 1 @gS2, float %0, i32 signext 43) 123 ret void 124} 125 126; CHECK-LABEL: name: call_test_byval_2Byte{{.*}} 127 128; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 129; 32BIT: renamable $r[[REG1:[0-9]+]] = LWZtoc @f, $r2 :: (load (s32) from got) 130; 32BIT-NEXT: renamable $f1 = LFS 0, killed renamable $r[[REG1]] :: (dereferenceable load (s32) from @f) 131; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 132; 32BIT-DAG: $r3 = LI 42 133; 32BIT-DAG: renamable $r[[REG2:[0-9]+]] = LWZtoc @gS2, $r2 :: (load (s32) from got) 134; 32BIT-DAG: renamable $r[[REG3:[0-9]+]] = LHZ 0, killed renamable $r[[REG2]] :: (load (s16)) 135; 32BIT-DAG: renamable $r5 = RLWINM killed renamable $r[[REG3]], 16, 0, 15 136; 32BIT-DAG: $f2 = COPY renamable $f1 137; 32BIT-DAG: $r7 = LI 43 138; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_2Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r5, implicit killed $f2, implicit killed $r7, implicit $r2, implicit-def $r1 139; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 140 141; CHECKASM-LABEL: .call_test_byval_2Byte: 142 143; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 144; ASM32: stwu 1, -64(1) 145; ASM32-DAG: li 3, 42 146; ASM32-DAG: lwz [[REG1:[0-9]+]], L..C{{[0-9]+}}(2) 147; ASM32-DAG: lfs 1, 0([[REG1]]) 148; ASM32-DAG: lwz [[REG2:[0-9]+]], L..C{{[0-9]+}}(2) 149; ASM32-DAG: lhz [[REG3:[0-9]+]], 0([[REG2]]) 150; ASM32-DAG: slwi 5, [[REG3]], 16 151; ASM32-DAG: fmr 2, 1 152; ASM32-DAG: li 7, 43 153; ASM32-NEXT: bl .test_byval_2Byte 154; ASM32-NEXT: nop 155; ASM32-NEXT: addi 1, 1, 64 156 157; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 158; 64BIT: renamable $x[[REG1:[0-9]+]] = LDtoc @f, $x2 :: (load (s64) from got) 159; 64BIT-NEXT: renamable $f1 = LFS 0, killed renamable $x[[REG1]] :: (dereferenceable load (s32) from @f) 160; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 161; 64BIT-DAG: $x3 = LI8 42 162; 64BIT-DAG: renamable $x[[REG2:[0-9]+]] = LDtoc @gS2, $x2 :: (load (s64) from got) 163; 64BIT-DAG: renamable $x[[REG3:[0-9]+]] = LHZ8 0, killed renamable $x[[REG2]] :: (load (s16)) 164; 64BIT-DAG: renamable $x5 = RLDICR killed renamable $x[[REG3]], 48, 15 165; 64BIT-DAG: $f2 = COPY renamable $f1 166; 64BIT-DAG: $x7 = LI8 43 167; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_2Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x5, implicit killed $f2, implicit killed $x7, implicit $x2, implicit-def $r1 168; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 169 170; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 171; ASM64: stdu 1, -112(1) 172; ASM64-DAG: std 0, 128(1) 173; ASM64-DAG: li 3, 42 174; ASM64-DAG: ld [[REG1:[0-9]+]], L..C{{[0-9]+}}(2) 175; ASM64-DAG: lfs 1, 0([[REG1]]) 176; ASM64-DAG: ld [[REG2:[0-9]+]], L..C{{[0-9]+}}(2) 177; ASM64-DAG: lhz [[REG3:[0-9]+]], 0([[REG2]]) 178; ASM64-DAG: sldi 5, [[REG3]], 48 179; ASM64-DAG: fmr 2, 1 180; ASM64-DAG: li 7, 43 181; ASM64-NEXT: bl .test_byval_2Byte 182; ASM64-NEXT: nop 183; ASM64-NEXT: addi 1, 1, 112 184 185define zeroext i8 @test_byval_2Byte(i32, float, ptr byval(%struct.S2) align 1 %s, float, i32) { 186entry: 187 %arrayidx = getelementptr inbounds %struct.S2, ptr %s, i32 0, i32 0, i32 1 188 %4 = load i8, ptr %arrayidx, align 1 189 ret i8 %4 190} 191 192; CHECK-LABEL: name: test_byval_2Byte 193; 32BIT: fixedStack: 194; 32BIT-NEXT: - { id: 0, type: default, offset: 32, size: 4, alignment: 16, stack-id: default, 195 196; 32BIT: bb.0.entry: 197; 32BIT-NEXT: liveins: $r5 198; 32BIT: STW killed renamable $r5, 0, %fixed-stack.0 :: (store (s32) into %fixed-stack.0, align 16) 199; 32BIT-NEXT: renamable $r3 = LBZ 1, %fixed-stack.0 :: (dereferenceable load (s8) 200 201; 64BIT: fixedStack: 202; 64BIT-NEXT: - { id: 0, type: default, offset: 64, size: 8, alignment: 16, stack-id: default, 203 204; 64BIT: bb.0.entry: 205; 64BIT-NEXT: liveins: $x5 206; 64BIT: STD killed renamable $x5, 0, %fixed-stack.0 :: (store (s64) into %fixed-stack.0, align 16) 207; 64BIT-NEXT: renamable $x3 = LBZ8 1, %fixed-stack.0 :: (dereferenceable load (s8) 208 209; CHECKASM-LABEL: .test_byval_2Byte: 210 211; ASM32: stw 5, 32(1) 212; ASM32-NEXT: lbz 3, 33(1) 213; ASM32-NEXT: blr 214 215; ASM64: std 5, 64(1) 216; ASM64-NEXT: lbz 3, 65(1) 217; ASM64-NEXT: blr 218 219 220%struct.S3 = type <{ i8, i16 }> 221@gS3 = external global %struct.S3, align 1 222 223define void @call_test_byval_3Byte() { 224entry: 225 %call = call zeroext i16 @test_byval_3Byte(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, ptr byval(%struct.S3) align 1 @gS3, i32 42) 226 ret void 227} 228 229; CHECK-LABEL: name: call_test_byval_3Byte{{.*}} 230 231; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 232; 32BIT: ADJCALLSTACKDOWN 60, 0, implicit-def dead $r1, implicit $r1 233; 32BIT-DAG: $r3 = LI 1 234; 32BIT-DAG: $r4 = LI 2 235; 32BIT-DAG: $r5 = LI 3 236; 32BIT-DAG: $r6 = LI 4 237; 32BIT-DAG: $r7 = LI 5 238; 32BIT-DAG: $r8 = LI 6 239; 32BIT-DAG: $r9 = LI 7 240; 32BIT-DAG: renamable $r[[REGADDR:[0-9]+]] = LWZtoc @gS3, $r2 :: (load (s32) from got) 241; 32BIT-DAG: renamable $r[[REG1:[0-9]+]] = LHZ 0, killed renamable $r[[REGADDR]] :: (load (s16)) 242; 32BIT-DAG: renamable $r[[REG2:[0-9]+]] = LBZ 2, renamable $r[[REGADDR]] :: (load (s8)) 243; 32BIT-DAG: renamable $r10 = RLWINM killed renamable $r[[REG2]], 8, 16, 23 244; 32BIT-DAG: renamable $r10 = RLWIMI killed renamable $r10, killed renamable $r[[REG1]], 16, 0, 15 245; 32BIT-DAG: renamable $r[[REG3:[0-9]+]] = LI 42 246; 32BIT-DAG: STW killed renamable $r[[REG3]], 56, $r1 :: (store (s32)) 247; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_3Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit killed $r9, implicit $r10, implicit $r2, implicit-def $r1 248; 32BIT-NEXT: ADJCALLSTACKUP 60, 0, implicit-def dead $r1, implicit $r1 249 250; CHECKASM-LABEL: .call_test_byval_3Byte: 251 252; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 253; ASM32: stwu 1, -64(1) 254; ASM32-DAG: li 3, 1 255; ASM32-DAG: li 4, 2 256; ASM32-DAG: li 5, 3 257; ASM32-DAG: li 6, 4 258; ASM32-DAG: li 7, 5 259; ASM32-DAG: li 8, 6 260; ASM32-DAG: li 9, 7 261; ASM32-DAG: lwz [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2) 262; ASM32-DAG: lhz [[REG1:[0-9]+]], 0([[REGADDR]]) 263; ASM32-DAG: lbz [[REG2:[0-9]+]], 2([[REGADDR]]) 264; ASM32-DAG: rlwinm 10, [[REG2]], 8, 16, 23 265; ASM32-DAG: rlwimi 10, [[REG1]], 16, 0, 15 266; ASM32-DAG: li [[REG3:[0-9]+]], 42 267; ASM32-DAG: stw [[REG3]], 56(1) 268; ASM32-NEXT: bl .test_byval_3Byte 269; ASM32-NEXT: nop 270 271; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 272; 64BIT: ADJCALLSTACKDOWN 120, 0, implicit-def dead $r1, implicit $r1 273; 64BIT-DAG: $x3 = LI8 1 274; 64BIT-DAG: $x4 = LI8 2 275; 64BIT-DAG: $x5 = LI8 3 276; 64BIT-DAG: $x6 = LI8 4 277; 64BIT-DAG: $x7 = LI8 5 278; 64BIT-DAG: $x8 = LI8 6 279; 64BIT-DAG: $x9 = LI8 7 280; 64BIT-DAG: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS3, $x2 :: (load (s64) from got) 281; 64BIT-DAG: renamable $x[[REG1:[0-9]+]] = LHZ8 0, killed renamable $x[[REGADDR]] :: (load (s16)) 282; 64BIT-DAG: renamable $x[[REG2:[0-9]+]] = LBZ8 2, renamable $x[[REGADDR]] :: (load (s8)) 283; 64BIT-DAG: renamable $x10 = RLDIC killed renamable $x[[REG2]], 40, 16 284; 64BIT-DAG: renamable $x10 = RLDIMI killed renamable $x10, killed renamable $x[[REG1]], 48, 0 285; 64BIT-DAG: $x[[REG3:[0-9]+]] = LI8 42 286; 64BIT-DAG: STD killed renamable $x[[REG3]], 112, $x1 :: (store (s64)) 287; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_3Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit $x10, implicit $x2, implicit-def $r1 288; 64BIT-NEXT: ADJCALLSTACKUP 120, 0, implicit-def dead $r1, implicit $r1 289 290; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 291; ASM64: stdu 1, -128(1) 292; ASM64-DAG: li 3, 1 293; ASM64-DAG: li 4, 2 294; ASM64-DAG: li 5, 3 295; ASM64-DAG: li 6, 4 296; ASM64-DAG: li 7, 5 297; ASM64-DAG: li 8, 6 298; ASM64-DAG: li 9, 7 299; ASM64-DAG: ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2) 300; ASM64-DAG: lhz [[REG1:[0-9]+]], 0([[REGADDR]]) 301; ASM64-DAG: lbz [[REG2:[0-9]+]], 2([[REGADDR]]) 302; ASM64-DAG: rldic 10, [[REG2]], 40, 16 303; ASM64-DAG: rldimi 10, [[REG1]], 48, 0 304; ASM64-DAG: li [[REG3:[0-9]+]], 42 305; ASM64-DAG: std [[REG3]], 112(1) 306; ASM64-NEXT: bl .test_byval_3Byte 307; ASM64-NEXT: nop 308 309 310define zeroext i16 @test_byval_3Byte(i32, i32, i32, i32, i32, i32, i32, ptr byval(%struct.S3) align 1 %s, i32) { 311entry: 312 %gep = getelementptr inbounds %struct.S3, ptr %s, i32 0, i32 1 313 %8 = load i16, ptr %gep, align 1 314 ret i16 %8 315} 316 317; CHECK-LABEL: name: test_byval_3Byte 318 319; 32BIT: fixedStack: 320; 32BIT-NEXT: - { id: 0, type: default, offset: 56, size: 4, alignment: 8, stack-id: default, 321; 32BIT: - { id: 1, type: default, offset: 52, size: 4, alignment: 4, stack-id: default, 322 323; 32BIT-LABEL: bb.0.entry: 324; 32BIT-NEXT: liveins: $r10 325; 32BIT: STW killed renamable $r10, 0, %fixed-stack.1 :: (store (s32) into %fixed-stack.1) 326; 32BIT-NEXT: renamable $r3 = LHZ 1, %fixed-stack.1 :: (dereferenceable load (s16) 327 328; 64BIT: fixedStack: 329; 64BIT-NEXT: - { id: 0, type: default, offset: 116, size: 4, alignment: 4, stack-id: default, 330; 64BIT: - { id: 1, type: default, offset: 104, size: 8, alignment: 8, stack-id: default, 331 332; 64BIT-LABEL: bb.0.entry: 333; 64BIT-NEXT: liveins: $x10 334; 64BIT: STD killed renamable $x10, 0, %fixed-stack.1 :: (store (s64) into %fixed-stack.1) 335; 64BIT-NEXT: renamable $x3 = LHZ8 1, %fixed-stack.1 :: (dereferenceable load (s16) 336 337; CHECKASM-LABEL: .test_byval_3Byte: 338 339; ASM32: stw 10, 52(1) 340; ASM32-NEXT: lhz 3, 53(1) 341; ASM32-NEXT: blr 342 343; ASM64: std 10, 104(1) 344; ASM64-NEXT: lhz 3, 105(1) 345; ASM64-NEXT: blr 346 347 348%struct.S4 = type { [4 x i8] } 349%struct.S4A = type { i32 } 350 351@gS4 = external global %struct.S4, align 1 352 353define void @call_test_byval_4Byte() { 354entry: 355 %s0 = alloca %struct.S0, align 8 356 %s4a = alloca %struct.S4A, align 8 357 %call = call signext i32 @test_byval_4Byte(ptr byval(%struct.S4) align 1 @gS4, ptr byval(%struct.S0) align 1 %s0, ptr byval(%struct.S4A) align 4 %s4a) 358 ret void 359} 360 361; CHECK-LABEL: name: call_test_byval_4Byte{{.*}} 362 363; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 364; 32BIT-NEXT: renamable $r[[REG:[0-9]+]] = LWZtoc @gS4, $r2 :: (load (s32) from got) 365; 32BIT-DAG: renamable $r3 = LWZ 0, killed renamable $r[[REG]] :: (load (s32)) 366; 32BIT-DAG: renamable $r4 = LWZ 0, %stack.1.s4a :: (load (s32) from %stack.1.s4a, align 8) 367; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_4Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r2, implicit-def $r1 368; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 369 370; CHECKASM-LABEL: .call_test_byval_4Byte: 371 372; ASM32: stwu 1, -80(1) 373; ASM32-NEXT: lwz [[REG:[0-9]+]], L..C{{[0-9]+}}(2) 374; ASM32-DAG: lwz 3, 0([[REG]]) 375; ASM32-DAG: lwz 4, 64(1) 376; ASM32-NEXT: bl .test_byval_4Byte 377; ASM32-NEXT: nop 378; ASM32-NEXT: addi 1, 1, 80 379 380; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 381; 64BIT-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS4, $x2 :: (load (s64) from got) 382; 64BIT-DAG: renamable $x[[LD1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load (s32)) 383; 64BIT-DAG: renamable $x[[LD2:[0-9]+]] = LWZ8 0, %stack.1.s4a :: (load (s32) from %stack.1.s4a, align 8) 384; 64BIT-DAG: renamable $x3 = RLDICR killed renamable $x[[LD1]], 32, 31 385; 64BIT-DAG: renamable $x4 = RLDICR killed renamable $x[[LD2]], 32, 31 386; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_4Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x2, implicit-def $r1 387; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 388 389; ASM64: stdu 1, -128(1) 390; ASM64-NEXT: ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2) 391; ASM64-DAG: lwz [[LD1:[0-9]+]], 0([[REGADDR]]) 392; ASM64-DAG: lwz [[LD2:[0-9]+]], 112(1) 393; ASM64-DAG: sldi 3, [[LD1]], 32 394; ASM64-DAG: sldi 4, [[LD2]], 32 395; ASM64-NEXT: bl .test_byval_4Byte 396; ASM64-NEXT: nop 397; ASM64-NEXT: addi 1, 1, 128 398 399 400define signext i32 @test_byval_4Byte(ptr byval(%struct.S4) align 1 %s, ptr byval(%struct.S0) align 1, ptr byval(%struct.S4A) align 4 %s4a) { 401entry: 402 %arrayidx = getelementptr inbounds %struct.S4, ptr %s, i32 0, i32 0, i32 3 403 %1 = load i8, ptr %arrayidx, align 1 404 %2 = load i32, ptr %s4a, align 4 405 %conv = zext i8 %1 to i32 406 %add = add nsw i32 %2, %conv 407 ret i32 %add 408} 409 410; CHECK-LABEL: name: test_byval_4Byte 411 412; 32BIT: fixedStack: 413; 32BIT-NEXT: - { id: 0, type: default, offset: 28, size: 4, alignment: 4, stack-id: default, 414; 32BIT-NEXT: isImmutable: false, isAliased: true, callee-saved-register: '', callee-saved-restored: true, 415; 32BIT: - { id: 1, type: default, offset: 28, size: 4, alignment: 4, stack-id: default, 416; 32BIT-NEXT: isImmutable: false, isAliased: true, callee-saved-register: '', callee-saved-restored: true, 417; 32BIT: - { id: 2, type: default, offset: 24, size: 4, alignment: 8, stack-id: default, 418; 32BIT-NEXT: isImmutable: false, isAliased: true, callee-saved-register: '', callee-saved-restored: true, 419 420; 32BIT: bb.0.entry: 421; 32BIT-NEXT: liveins: $r3 422; 32BIT: STW renamable $r3, 0, %fixed-stack.2 :: (store (s32) into %fixed-stack.2, align 8) 423; 32BIT-DAG: STW killed renamable $r4, 0, %fixed-stack.0 :: (store (s32) into %fixed-stack.0) 424; 32BIT-DAG: renamable $r[[SCRATCH:[0-9]+]] = RLWINM killed renamable $r3, 0, 24, 31 425; 32BIT-DAG: renamable $r3 = nsw ADD4 renamable $r4, killed renamable $r[[SCRATCH]] 426; 32BIT: BLR 427 428; 64BIT: fixedStack: 429; 64BIT-NEXT: - { id: 0, type: default, offset: 56, size: 8, alignment: 8, stack-id: default, 430; 64BIT-NEXT: isImmutable: false, isAliased: true, callee-saved-register: '', callee-saved-restored: true, 431; 64BIT: - { id: 1, type: default, offset: 56, size: 8, alignment: 8, stack-id: default, 432; 64BIT-NEXT: isImmutable: false, isAliased: true, callee-saved-register: '', callee-saved-restored: true, 433; 64BIT: - { id: 2, type: default, offset: 48, size: 8, alignment: 16, stack-id: default, 434; 64BIT-NEXT: isImmutable: false, isAliased: true, callee-saved-register: '', callee-saved-restored: true, 435 436; 64BIT: bb.0.entry: 437; 64BIT-NEXT: liveins: $x3 438; 64BIT: STD killed renamable $x3, 0, %fixed-stack.2 :: (store (s64) into %fixed-stack.2, align 16) 439; 64BIT: STD renamable $x4, 0, %fixed-stack.0 :: (store (s64) into %fixed-stack.0) 440; 64BIT-DAG: renamable $r[[SCRATCH1:[0-9]+]] = LBZ 3, %fixed-stack.2 :: (dereferenceable load (s8) 441; 64BIT-DAG: renamable $x[[SCRATCH2:[0-9]+]] = RLDICL killed renamable $x4, 32, 32 442; 64BIT-NEXT: renamable $r[[SCRATCH3:[0-9]+]] = nsw ADD4 renamable $r[[SCRATCH2]], killed renamable $r[[SCRATCH1]], implicit killed $x[[SCRATCH2]] 443; 64BIT-NEXT: renamable $x3 = EXTSW_32_64 killed renamable $r[[SCRATCH3]] 444; 64BIT-NEXT: BLR8 445 446; CHECKASM-LABEL: .test_byval_4Byte: 447 448; ASM32: stw 3, 24(1) 449; ASM32-DAG: stw 4, 28(1) 450; ASM32-DAG: clrlwi [[SCRATCH:[0-9]+]], 3, 24 451; ASM32-DAG: add 3, 4, [[SCRATCH]] 452; ASM32-NEXT: blr 453 454; ASM64: std 3, 48(1) 455; ASM64-NEXT: lbz [[SCRATCH1:[0-9]+]], 51(1) 456; ASM64-NEXT: std 4, 56(1) 457; ASM64-NEXT: rldicl [[SCRATCH2:[0-9]+]], 4, 32, 32 458; ASM64-NEXT: add [[SCRATCH3:[0-9]+]], [[SCRATCH2]], [[SCRATCH1]] 459; ASM64-NEXT: extsw 3, [[SCRATCH3]] 460; ASM64-NEXT: blr 461 462 463%struct.S5 = type { [5 x i8] } 464 465@gS5 = external global %struct.S5, align 1 466 467define void @call_test_byval_5Byte() { 468entry: 469 %call = call zeroext i8 @test_byval_5Byte(ptr byval(%struct.S5) align 1 @gS5) 470 ret void 471} 472 473declare zeroext i8 @test_byval_5Byte(ptr byval(%struct.S5) align 1) 474 475; CHECK-LABEL: name: call_test_byval_5Byte{{.*}} 476 477; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 478; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 479; 32BIT-NEXT: renamable $r[[REGADDR:[0-9]+]] = LWZtoc @gS5, $r2 :: (load (s32) from got) 480; 32BIT-DAG: renamable $r[[REG1:[0-9]+]] = LBZ 4, renamable $r[[REGADDR]] :: (load (s8)) 481; 32BIT-DAG: renamable $r3 = LWZ 0, killed renamable $r[[REGADDR]] :: (load (s32)) 482; 32BIT-DAG: renamable $r4 = RLWINM killed renamable $r[[REG1]], 24, 0, 7 483; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_5Byte[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r2, implicit-def $r1 484; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 485 486; CHECKASM-LABEL: .call_test_byval_5Byte: 487 488; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 489; ASM32: stwu 1, -64(1) 490; ASM32-NEXT: lwz [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2) 491; ASM32-DAG: lbz [[REG1:[0-9]+]], 4([[REGADDR]]) 492; ASM32-DAG: lwz 3, 0([[REGADDR]]) 493; ASM32-DAG: slwi 4, [[REG1]], 24 494; ASM32-NEXT: bl .test_byval_5Byte[PR] 495; ASM32-NEXT: nop 496 497; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 498; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 499; 64BIT-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS5, $x2 :: (load (s64) from got) 500; 64BIT-DAG: renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load (s32)) 501; 64BIT-DAG: renamable $x[[REG2:[0-9]+]] = LBZ8 4, renamable $x[[REGADDR]] :: (load (s8)) 502; 64BIT-DAG: renamable $x3 = RLWINM8 killed renamable $x[[REG2]], 24, 0, 7 503; 64BIT-DAG: renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0 504; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_5Byte[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1 505; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 506 507; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 508; ASM64: stdu 1, -112(1) 509; ASM64-NEXT: ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2) 510; ASM64-DAG: lwz [[REG1:[0-9]+]], 0([[REGADDR]]) 511; ASM64-DAG: lbz [[REG2:[0-9]+]], 4([[REGADDR]]) 512; ASM64-DAG: rlwinm 3, [[REG2]], 24, 0, 7 513; ASM64-DAG: rldimi 3, [[REG1]], 32, 0 514; ASM64-NEXT: bl .test_byval_5Byte[PR] 515; ASM64-NEXT: nop 516 517 518%struct.S6 = type { [6 x i8] } 519 520@gS6 = external global %struct.S6, align 1 521 522define void @call_test_byval_6Byte() { 523entry: 524 %call = call zeroext i8 @test_byval_6Byte(ptr byval(%struct.S6) align 1 @gS6) 525 ret void 526} 527 528declare zeroext i8 @test_byval_6Byte(ptr byval(%struct.S6) align 1) 529 530; CHECK-LABEL: name: call_test_byval_6Byte{{.*}} 531 532; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 533; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 534; 32BIT-NEXT: renamable $r[[REGADDR:[0-9]+]] = LWZtoc @gS6, $r2 :: (load (s32) from got) 535; 32BIT-DAG: renamable $r[[REG1:[0-9]+]] = LHZ 4, renamable $r[[REGADDR]] :: (load (s16)) 536; 32BIT-DAG: renamable $r3 = LWZ 0, killed renamable $r[[REGADDR]] :: (load (s32)) 537; 32BIT-DAG: renamable $r4 = RLWINM killed renamable $r[[REG1]], 16, 0, 15 538; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_6Byte[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r2, implicit-def $r1 539; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 540 541; CHECKASM-LABEL: .call_test_byval_6Byte: 542 543; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 544; ASM32: stwu 1, -64(1) 545; ASM32-NEXT: lwz [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2) 546; ASM32-DAG: lhz [[REG1:[0-9]+]], 4([[REGADDR]]) 547; ASM32-DAG: lwz 3, 0([[REGADDR]]) 548; ASM32-DAG: slwi 4, [[REG1]], 16 549; ASM32-NEXT: bl .test_byval_6Byte[PR] 550; ASM32-NEXT: nop 551 552; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 553; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 554; 64BIT-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS6, $x2 :: (load (s64) from got) 555; 64BIT-DAG: renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load (s32)) 556; 64BIT-DAG: renamable $x[[REG2:[0-9]+]] = LHZ8 4, renamable $x[[REGADDR]] :: (load (s16)) 557; 64BIT-DAG: renamable $x3 = RLWINM8 killed renamable $x[[REG2]], 16, 0, 15 558; 64BIT-DAG: renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0 559; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_6Byte[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1 560; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 561 562; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 563; ASM64: stdu 1, -112(1) 564; ASM64-NEXT: ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2) 565; ASM64-DAG: lwz [[REG1:[0-9]+]], 0([[REGADDR]]) 566; ASM64-DAG: lhz [[REG2:[0-9]+]], 4([[REGADDR]]) 567; ASM64-DAG: rlwinm 3, [[REG2]], 16, 0, 15 568; ASM64-DAG: rldimi 3, [[REG1]], 32, 0 569; ASM64-NEXT: bl .test_byval_6Byte[PR] 570; ASM64-NEXT: nop 571 572 573%struct.S7 = type { [7 x i8] } 574 575@gS7 = external global %struct.S7, align 1 576 577define void @call_test_byval_7Byte() { 578entry: 579 %call = call zeroext i8 @test_byval_7Byte(ptr byval(%struct.S7) align 1 @gS7) 580 ret void 581} 582 583declare zeroext i8 @test_byval_7Byte(ptr byval(%struct.S7) align 1) 584 585; CHECK-LABEL: name: call_test_byval_7Byte{{.*}} 586 587; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 588; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 589; 32BIT-NEXT: renamable $r[[REGADDR:[0-9]+]] = LWZtoc @gS7, $r2 :: (load (s32) from got) 590; 32BIT-DAG: renamable $r3 = LWZ 0, killed renamable $r[[REGADDR]] :: (load (s32)) 591; 32BIT-DAG: renamable $r[[REG1:[0-9]+]] = LHZ 4, renamable $r[[REGADDR]] :: (load (s16)) 592; 32BIT-DAG: renamable $r[[REG2:[0-9]+]] = LBZ 6, renamable $r[[REGADDR]] :: (load (s8)) 593; 32BIT-DAG: renamable $r4 = RLWINM killed renamable $r[[REG2]], 8, 16, 23 594; 32BIT-DAG: renamable $r4 = RLWIMI killed renamable $r4, killed renamable $r[[REG1]], 16, 0, 15 595; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_7Byte[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r2, implicit-def $r1 596; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 597 598; CHECKASM-LABEL: .call_test_byval_7Byte: 599 600; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 601; ASM32: stwu 1, -64(1) 602; ASM32-NEXT: lwz [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2) 603; ASM32-DAG: lwz 3, 0([[REGADDR]]) 604; ASM32-DAG: lhz [[REG1:[0-9]+]], 4([[REGADDR]]) 605; ASM32-DAG: lbz [[REG2:[0-9]+]], 6([[REGADDR]]) 606; ASM32-DAG: rlwinm 4, [[REG2]], 8, 16, 23 607; ASM32-DAG: rlwimi 4, [[REG1]], 16, 0, 15 608; ASM32-NEXT: bl .test_byval_7Byte[PR] 609; ASM32-NEXT: nop 610 611; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 612; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 613; 64BIT-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS7, $x2 :: (load (s64) from got) 614; 64BIT-DAG: renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load (s32)) 615; 64BIT-DAG: renamable $x[[REG2:[0-9]+]] = LHZ8 4, renamable $x[[REGADDR]] :: (load (s16)) 616; 64BIT-DAG: renamable $x[[REG3:[0-9]+]] = LBZ8 6, renamable $x[[REGADDR]] :: (load (s8)) 617; 64BIT-DAG: renamable $x3 = RLWINM8 killed renamable $x[[REG3]], 8, 16, 23 618; 64BIT-DAG: renamable $x3 = RLWIMI8 killed renamable $x3, killed renamable $x[[REG2]], 16, 0, 15 619; 64BIT-DAG: renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0 620; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_7Byte[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1 621; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 622 623; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 624; ASM64: stdu 1, -112(1) 625; ASM64-NEXT: ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2) 626; ASM64-DAG: lwz [[REG1:[0-9]+]], 0([[REGADDR]]) 627; ASM64-DAG: lhz [[REG2:[0-9]+]], 4([[REGADDR]]) 628; ASM64-DAG: lbz [[REG3:[0-9]+]], 6([[REGADDR]]) 629; ASM64-DAG: rlwinm 3, [[REG3]], 8, 16, 23 630; ASM64-DAG: rlwimi 3, [[REG2]], 16, 0, 15 631; ASM64-DAG: rldimi 3, [[REG1]], 32, 0 632; ASM64-NEXT: bl .test_byval_7Byte[PR] 633; ASM64-NEXT: nop 634 635 636%struct.S8 = type { [8 x i8] } 637 638@gS8 = external global %struct.S8, align 1 639 640define void @call_test_byval_8Byte() { 641entry: 642 %call = call zeroext i8 @test_byval_8Byte(ptr byval(%struct.S8) align 1 @gS8) 643 ret void 644} 645 646declare zeroext i8 @test_byval_8Byte(ptr byval(%struct.S8) align 1) 647 648; CHECK-LABEL: name: call_test_byval_8Byte{{.*}} 649 650; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 651; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 652; 32BIT-NEXT: renamable $r[[REGADDR:[0-9]+]] = LWZtoc @gS8, $r2 :: (load (s32) from got) 653; 32BIT-DAG: renamable $r3 = LWZ 0, killed renamable $r[[REGADDR]] :: (load (s32)) 654; 32BIT-DAG: renamable $r4 = LWZ 4, renamable $r[[REGADDR]] :: (load (s32)) 655; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_8Byte[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r2, implicit-def $r1 656; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 657 658; CHECKASM-LABEL: .call_test_byval_8Byte: 659 660; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 661; ASM32: stwu 1, -64(1) 662; ASM32-NEXT: lwz [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2) 663; ASM32-DAG: lwz 3, 0([[REGADDR]]) 664; ASM32-DAG: lwz 4, 4([[REGADDR]]) 665; ASM32-NEXT: bl .test_byval_8Byte[PR] 666; ASM32-NEXT: nop 667 668; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 669; 64BIT-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS8, $x2 :: (load (s64) from got) 670; 64BIT-NEXT: renamable $x3 = LD 0, killed renamable $x[[REGADDR]] :: (load (s64)) 671; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_8Byte[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1 672; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 673 674; ASM64: stdu 1, -112(1) 675; ASM64-NEXT: ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2) 676; ASM64-NEXT: std 0, 128(1) 677; ASM64-NEXT: ld 3, 0([[REGADDR]]) 678; ASM64-NEXT: bl .test_byval_8Byte[PR] 679; ASM64-NEXT: nop 680 681 682%struct.S32 = type { [32 x i8] } 683 684@gS32 = external global %struct.S32, align 1 685 686define void @call_test_byval_32Byte() { 687entry: 688 %call = call zeroext i8 @test_byval_32Byte(ptr byval(%struct.S32) align 1 @gS32) 689 ret void 690} 691 692; CHECK-LABEL: name: call_test_byval_32Byte{{.*}} 693 694; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 695; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 696; 32BIT-NEXT: renamable $r[[REGADDR:[0-9]+]] = LWZtoc @gS32, $r2 :: (load (s32) from got) 697; 32BIT-DAG: renamable $r3 = LWZ 0, killed renamable $r[[REGADDR]] :: (load (s32)) 698; 32BIT-DAG: renamable $r4 = LWZ 4, renamable $r[[REGADDR]] :: (load (s32)) 699; 32BIT-DAG: renamable $r5 = LWZ 8, renamable $r[[REGADDR]] :: (load (s32)) 700; 32BIT-DAG: renamable $r6 = LWZ 12, renamable $r[[REGADDR]] :: (load (s32)) 701; 32BIT-DAG: renamable $r7 = LWZ 16, renamable $r[[REGADDR]] :: (load (s32)) 702; 32BIT-DAG: renamable $r8 = LWZ 20, renamable $r[[REGADDR]] :: (load (s32)) 703; 32BIT-DAG: renamable $r9 = LWZ 24, renamable $r[[REGADDR]] :: (load (s32)) 704; 32BIT-DAG: renamable $r10 = LWZ 28, renamable $r[[REGADDR]] :: (load (s32)) 705; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_32Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1 706; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 707 708; CHECKASM-LABEL: .call_test_byval_32Byte: 709 710; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 711; ASM32: stwu 1, -64(1) 712; ASM32-NEXT: lwz [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2) 713; ASM32-DAG: lwz 3, 0([[REGADDR]]) 714; ASM32-DAG: lwz 4, 4([[REGADDR]]) 715; ASM32-DAG: lwz 5, 8([[REGADDR]]) 716; ASM32-DAG: lwz 6, 12([[REGADDR]]) 717; ASM32-DAG: lwz 7, 16([[REGADDR]]) 718; ASM32-DAG: lwz 8, 20([[REGADDR]]) 719; ASM32-DAG: lwz 9, 24([[REGADDR]]) 720; ASM32-DAG: lwz 10, 28([[REGADDR]]) 721; ASM32-NEXT: bl .test_byval_32Byte 722; ASM32-NEXT: nop 723 724; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 725; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 726; 64BIT-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS32, $x2 :: (load (s64) from got) 727; 64BIT-DAG: renamable $x3 = LD 0, killed renamable $x[[REGADDR]] :: (load (s64)) 728; 64BIT-DAG: renamable $x4 = LD 8, renamable $x[[REGADDR]] :: (load (s64)) 729; 64BIT-DAG: renamable $x5 = LD 16, renamable $x[[REGADDR]] :: (load (s64)) 730; 64BIT-DAG: renamable $x6 = LD 24, renamable $x[[REGADDR]] :: (load (s64)) 731; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_32Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x2, implicit-def $r1 732; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 733 734; ASM64: stdu 1, -112(1) 735; ASM64-NEXT: ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2) 736; ASM64-DAG: ld 3, 0([[REGADDR]]) 737; ASM64-DAG: ld 4, 8([[REGADDR]]) 738; ASM64-DAG: ld 5, 16([[REGADDR]]) 739; ASM64-DAG: ld 6, 24([[REGADDR]]) 740; ASM64-NEXT: bl .test_byval_32Byte 741; ASM64-NEXT: nop 742 743define zeroext i8 @test_byval_32Byte(ptr byval(%struct.S32) align 1 %s) { 744entry: 745 %arrayidx = getelementptr inbounds %struct.S32, ptr %s, i32 0, i32 0, i32 21 746 %0 = load i8, ptr %arrayidx, align 1 747 ret i8 %0 748} 749 750; The ByVal handling produces dead stores. See `LowerFormalArguments_AIX` for 751; details on why. 752 753; CHECK-LABEL: name: test_byval_32Byte 754 755; 32BIT: fixedStack: 756; 32BIT-NEXT: - { id: 0, type: default, offset: 24, size: 32, alignment: 8, stack-id: default, 757; 32BIT-NEXT: isImmutable: false, isAliased: true, callee-saved-register: '', callee-saved-restored: true, 758 759; 32BIT: bb.0.entry: 760; 32BIT-NEXT: liveins: $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10 761; 32BIT: STW killed renamable $r8, 20, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 20 762; 32BIT-DAG: STW killed renamable $r3, 0, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 763; 32BIT-DAG: STW killed renamable $r4, 4, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 4 764; 32BIT-DAG: STW killed renamable $r5, 8, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 8 765; 32BIT-DAG: STW killed renamable $r6, 12, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 12 766; 32BIT-DAG: STW killed renamable $r7, 16, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 16 767; 32BIT: renamable $r3 = LBZ 21, %fixed-stack.0 :: (dereferenceable load (s8) 768; 32BIT-DAG: STW killed renamable $r9, 24, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 24 769; 32BIT-DAG: STW killed renamable $r10, 28, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 28 770; 32BIT: BLR 771 772; 64BIT: fixedStack: 773; 64BIT-NEXT: - { id: 0, type: default, offset: 48, size: 32, alignment: 16, stack-id: default, 774; 64BIT-NEXT: isImmutable: false, isAliased: true, callee-saved-register: '', callee-saved-restored: true, 775 776; 64BIT: bb.0.entry: 777; 64BIT-NEXT: liveins: $x3, $x4, $x5, $x6 778; 64BIT: STD killed renamable $x5, 16, %fixed-stack.0 :: (store (s64) into %fixed-stack.0 + 16 779; 64BIT-DAG: STD killed renamable $x3, 0, %fixed-stack.0 :: (store (s64) into %fixed-stack.0 780; 64BIT-NEXT: renamable $x3 = LBZ8 21, %fixed-stack.0 :: (dereferenceable load (s8) 781; 64BIT-DAG: STD killed renamable $x4, 8, %fixed-stack.0 :: (store (s64) into %fixed-stack.0 + 8 782; 64BIT-DAG: STD killed renamable $x6, 24, %fixed-stack.0 :: (store (s64) into %fixed-stack.0 + 24 783; 64BIT-NEXT: BLR8 784 785; CHECKASM-LABEL: .test_byval_32Byte: 786 787; ASM32: stw 8, 44(1) 788; ASM32: stw 3, 24(1) 789; ASM32-DAG: lbz 3, 45(1) 790; ASM32-DAG: stw 4, 28(1) 791; ASM32-DAG: stw 5, 32(1) 792; ASM32-DAG: stw 6, 36(1) 793; ASM32-DAG: stw 7, 40(1) 794; ASM32-DAG: stw 9, 48(1) 795; ASM32-DAG: stw 10, 52(1) 796; ASM32-NEXT: blr 797 798; ASM64: std 5, 64(1) 799; ASM64: std 3, 48(1) 800; ASM64-DAG: lbz 3, 69(1) 801; ASM64-DAG: std 4, 56(1) 802; ASM64-DAG: std 6, 72(1) 803; ASM64-NEXT: blr 804 805%struct.S31 = type <{ float, i32, i64, double, i32, i16, i8 }> 806 807@gS31 = external global %struct.S31, align 1 808 809define void @call_test_byval_31Byte() { 810entry: 811 %call = call double @test_byval_31Byte(ptr byval(%struct.S31) align 1 @gS31) 812 ret void 813} 814 815 816; CHECK-LABEL: name: call_test_byval_31Byte{{.*}} 817 818; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 819; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 820; 32BIT-NEXT: renamable $r[[REGADDR:[0-9]+]] = LWZtoc @gS31, $r2 :: (load (s32) from got) 821; 32BIT-DAG: renamable $r3 = LWZ 0, killed renamable $r[[REGADDR]] :: (load (s32)) 822; 32BIT-DAG: renamable $r4 = LWZ 4, renamable $r[[REGADDR]] :: (load (s32)) 823; 32BIT-DAG: renamable $r5 = LWZ 8, renamable $r[[REGADDR]] :: (load (s32)) 824; 32BIT-DAG: renamable $r6 = LWZ 12, renamable $r[[REGADDR]] :: (load (s32)) 825; 32BIT-DAG: renamable $r7 = LWZ 16, renamable $r[[REGADDR]] :: (load (s32)) 826; 32BIT-DAG: renamable $r8 = LWZ 20, renamable $r[[REGADDR]] :: (load (s32)) 827; 32BIT-DAG: renamable $r9 = LWZ 24, renamable $r[[REGADDR]] :: (load (s32)) 828; 32BIT-DAG: renamable $r[[REG:[0-9]+]] = LHZ 28, renamable $r[[REGADDR]] :: (load (s16)) 829; 32BIT-DAG: renamable $r10 = LBZ 30, renamable $r[[REGADDR]] :: (load (s8)) 830; 32BIT-DAG: renamable $r10 = RLWINM killed renamable $r10, 8, 16, 23 831; 32BIT-DAG: renamable $r10 = RLWIMI killed renamable $r10, killed renamable $r[[REG]], 16, 0, 15 832; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_31Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1 833; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 834 835; CHECKASM-LABEL: .call_test_byval_31Byte: 836 837; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 838; ASM32: stwu 1, -64(1) 839; ASM32-NEXT: lwz [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2) 840; ASM32-DAG: lwz 3, 0([[REGADDR]]) 841; ASM32-DAG: lwz 4, 4([[REGADDR]]) 842; ASM32-DAG: lwz 5, 8([[REGADDR]]) 843; ASM32-DAG: lwz 6, 12([[REGADDR]]) 844; ASM32-DAG: lwz 7, 16([[REGADDR]]) 845; ASM32-DAG: lwz 8, 20([[REGADDR]]) 846; ASM32-DAG: lwz 9, 24([[REGADDR]]) 847; ASM32-DAG: lbz 10, 30([[REGADDR]]) 848; ASM32-DAG: lhz [[REG:[0-9]+]], 28([[REGADDR]]) 849; ASM32-DAG: rlwinm 10, 10, 8, 16, 23 850; ASM32-DAG: rlwimi 10, [[REG]], 16, 0, 15 851; ASM32-NEXT: bl .test_byval_31Byte 852; ASM32-NEXT: nop 853 854; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 855; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 856; 64BIT-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS31, $x2 :: (load (s64) from got) 857; 64BIT-DAG: renamable $x3 = LD 0, killed renamable $x[[REGADDR]] :: (load (s64)) 858; 64BIT-DAG: renamable $x4 = LD 8, renamable $x[[REGADDR]] :: (load (s64)) 859; 64BIT-DAG: renamable $x5 = LD 16, renamable $x[[REGADDR]] :: (load (s64)) 860; 64BIT-DAG: renamable $x[[REG1:[0-9]+]] = LWZ8 24, renamable $x[[REGADDR]] :: (load (s32)) 861; 64BIT-DAG: renamable $x[[REG2:[0-9]+]] = LHZ8 28, renamable $x[[REGADDR]] :: (load (s16)) 862; 64BIT-DAG: renamable $x[[REG3:[0-9]+]] = LBZ8 30, renamable $x[[REGADDR]] :: (load (s8)) 863; 64BIT-DAG: renamable $x6 = RLWINM8 killed renamable $x[[REG3]], 8, 16, 23 864; 64BIT-DAG: renamable $x6 = RLWIMI8 killed renamable $x6, killed renamable $x[[REG2]], 16, 0, 15 865; 64BIT-DAG: renamable $x6 = RLDIMI killed renamable $x6, killed renamable $x[[REG1]], 32, 0 866; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_31Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x2, implicit-def $r1 867; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 868 869; ASM64: stdu 1, -112(1) 870; ASM64-NEXT: ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2) 871; ASM64-DAG: ld 3, 0([[REGADDR]]) 872; ASM64-DAG: ld 4, 8([[REGADDR]]) 873; ASM64-DAG: ld 5, 16([[REGADDR]]) 874; ASM64-DAG: lwz [[REG1:[0-9]+]], 24([[REGADDR]]) 875; ASM64-DAG: lhz [[REG2:[0-9]+]], 28([[REGADDR]]) 876; ASM64-DAG: lbz [[REG3:[0-9]+]], 30([[REGADDR]]) 877; ASM64-DAG: rlwinm 6, [[REG3]], 8, 16, 23 878; ASM64-DAG: rlwimi 6, [[REG2]], 16, 0, 15 879; ASM64-DAG: rldimi 6, [[REG1]], 32, 0 880; ASM64-NEXT: bl .test_byval_31Byte 881; ASM64-NEXT: nop 882 883 884 885define double @test_byval_31Byte(ptr byval(%struct.S31) align 1 %s) { 886entry: 887 %gep = getelementptr inbounds %struct.S31, ptr %s, i32 0, i32 3 888 %load = load double, ptr %gep, align 1 889 ret double %load 890} 891 892; CHECK-LABEL: name: test_byval_31Byte 893 894; 32BIT: fixedStack: 895; 32BIT-NEXT: - { id: 0, type: default, offset: 24, size: 32, alignment: 8, stack-id: default, 896; 32BIT-NEXT: isImmutable: false, isAliased: true, callee-saved-register: '', callee-saved-restored: true, 897 898; 32BIT: bb.0.entry: 899; 32BIT-NEXT: liveins: $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10 900; 32BIT-DAG: STW killed renamable $r3, 0, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 901; 32BIT-DAG: STW killed renamable $r4, 4, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 4 902; 32BIT-DAG: STW killed renamable $r5, 8, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 8 903; 32BIT-DAG: STW killed renamable $r6, 12, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 12 904; 32BIT-DAG: STW killed renamable $r7, 16, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 16 905; 32BIT-DAG: STW killed renamable $r8, 20, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 20 906; 32BIT-NEXT: renamable $f1 = LFD 16, %fixed-stack.0 :: (dereferenceable load (s64) 907; 32BIT-DAG: STW killed renamable $r9, 24, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 24 908; 32BIT-DAG: STW killed renamable $r10, 28, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 28 909; 32BIT-NEXT: BLR 910 911; 64BIT: fixedStack: 912; 64BIT-NEXT: - { id: 0, type: default, offset: 48, size: 32, alignment: 16, stack-id: default, 913; 64BIT-NEXT: isImmutable: false, isAliased: true, callee-saved-register: '', callee-saved-restored: true, 914 915; 64BIT: bb.0.entry: 916; 64BIT-NEXT: liveins: $x3, $x4, $x5, $x6 917; 64BIT-DAG: STD killed renamable $x3, 0, %fixed-stack.0 :: (store (s64) into %fixed-stack.0 918; 64BIT-DAG: STD killed renamable $x5, 16, %fixed-stack.0 :: (store (s64) into %fixed-stack.0 + 16 919; 64BIT-NEXT: renamable $f1 = LFD 16, %fixed-stack.0 :: (dereferenceable load (s64) 920; 64BIT-DAG: STD killed renamable $x4, 8, %fixed-stack.0 :: (store (s64) into %fixed-stack.0 + 8 921; 64BIT-DAG: STD killed renamable $x6, 24, %fixed-stack.0 :: (store (s64) into %fixed-stack.0 + 24 922; 64BIT-NEXT: BLR8 923 924; ASM32-LABEL: .test_byval_31Byte: 925 926; ASM32-DAG: stw 8, 44(1) 927; ASM32: stw 7, 40(1) 928; ASM32-DAG: lfd 1, 40(1) 929; ASM32-DAG: stw 3, 24(1) 930; ASM32-DAG: stw 4, 28(1) 931; ASM32-DAG: stw 5, 32(1) 932; ASM32-DAG: stw 6, 36(1) 933; ASM32-DAG: stw 9, 48(1) 934; ASM32-DAG: stw 10, 52(1) 935; ASM32-NEXT: blr 936 937; ASM64: std 5, 64(1) 938; ASM64: lfd 1, 64(1) 939; ASM64-DAG: std 3, 48(1) 940; ASM64-DAG: std 4, 56(1) 941; ASM64-DAG: std 6, 72(1) 942; ASM64-NEXT: blr 943 944%struct.F = type { float, float, float } 945 946define i32 @call_test_byval_homogeneous_float_struct() { 947entry: 948 %s = alloca %struct.F, align 8 949 call void @llvm.memset.p0.i32(ptr align 4 %s, i8 0, i32 12, i1 false) 950 %call = call i32 @test_byval_homogeneous_float_struct(ptr byval(%struct.F) align 4 %s) 951 ret i32 %call 952} 953 954declare void @llvm.memset.p0.i32(ptr nocapture writeonly, i8, i32, i1 immarg) 955 956declare i32 @test_byval_homogeneous_float_struct(ptr byval(%struct.F) align 4) 957 958; CHECK-LABEL: name: call_test_byval_homogeneous_float_struct{{.*}} 959 960; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 961; 32BIT-DAG: renamable $r4 = LWZ 4, %stack.0.s :: (load (s32) from %stack.0.s + 4) 962; 32BIT-DAG: renamable $r5 = LWZ 8, %stack.0.s :: (load (s32) from %stack.0.s + 8, align 8) 963; 32BIT-DAG: $r3 = LI 0 964; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_homogeneous_float_struct[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r2, implicit-def $r1, implicit-def $r3 965; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 966 967; CHECKASM-LABEL: .call_test_byval_homogeneous_float_struct: 968 969; ASM32: stwu 1, -80(1) 970; ASM32-DAG: lwz 4, 68(1) 971; ASM32-DAG: lwz 5, 72(1) 972; ASM32-DAG: stw 3, 64(1) 973; ASM32-NEXT: bl .test_byval_homogeneous_float_struct[PR] 974; ASM32-NEXT: nop 975 976; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 977; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 978; 64BIT: renamable $x3 = LWZ8 8, %stack.0.s :: (load (s32) from %stack.0.s + 8, align 8) 979; 64BIT-NEXT: renamable $x4 = RLDICR killed renamable $x3, 32, 31 980; 64BIT-NEXT: $x3 = LI8 0 981; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_homogeneous_float_struct[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x2, implicit-def $r1, implicit-def $x3 982; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 983 984; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 985; ASM64: stdu 1, -128(1) 986; ASM64: lwz 3, 120(1) 987; ASM64-NEXT: sldi 4, 3, 32 988; ASM64-NEXT: li 3, 0 989; ASM64-NEXT: bl .test_byval_homogeneous_float_struct[PR] 990; ASM64-NEXT: nop 991