1; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \ 2; RUN: -ppc-asm-full-reg-names -mcpu=pwr9 < %s | FileCheck %s 3; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \ 4; RUN: -ppc-asm-full-reg-names -mcpu=pwr9 < %s | FileCheck %s 5 6define i64 @addze1(i64 %X, i64 %Z) { 7; CHECK-LABEL: addze1: 8; CHECK: # %bb.0: 9; CHECK-NEXT: addic [[REG1:r[0-9]+]], [[REG1]], -1 10; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 11; CHECK-NEXT: blr 12 %cmp = icmp ne i64 %Z, 0 13 %conv1 = zext i1 %cmp to i64 14 %add = add nsw i64 %conv1, %X 15 ret i64 %add 16} 17 18define i64 @addze2(i64 %X, i64 %Z) { 19; CHECK-LABEL: addze2: 20; CHECK: # %bb.0: 21; CHECK-NEXT: subfic [[REG1:r[0-9]+]], [[REG1]], 0 22; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 23; CHECK-NEXT: blr 24 %cmp = icmp eq i64 %Z, 0 25 %conv1 = zext i1 %cmp to i64 26 %add = add nsw i64 %conv1, %X 27 ret i64 %add 28} 29 30define i64 @addze3(i64 %X, i64 %Z) { 31; CHECK-LABEL: addze3: 32; CHECK: # %bb.0: 33; CHECK-NEXT: addi [[REG1:r[0-9]+]], [[REG1]], -32768 34; CHECK-NEXT: addic [[REG1]], [[REG1]], -1 35; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 36; CHECK-NEXT: blr 37 %cmp = icmp ne i64 %Z, 32768 38 %conv1 = zext i1 %cmp to i64 39 %add = add nsw i64 %conv1, %X 40 ret i64 %add 41} 42 43define i64 @addze4(i64 %X, i64 %Z) { 44; CHECK-LABEL: addze4: 45; CHECK: # %bb.0: 46; CHECK-NEXT: addi [[REG1:r[0-9]+]], [[REG1]], -32768 47; CHECK-NEXT: subfic [[REG1]], [[REG1]], 0 48; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 49; CHECK-NEXT: blr 50 %cmp = icmp eq i64 %Z, 32768 51 %conv1 = zext i1 %cmp to i64 52 %add = add nsw i64 %conv1, %X 53 ret i64 %add 54} 55 56define i64 @addze5(i64 %X, i64 %Z) { 57; CHECK-LABEL: addze5: 58; CHECK: # %bb.0: 59; CHECK-NEXT: addi [[REG1:r[0-9]+]], [[REG1]], 32767 60; CHECK-NEXT: addic [[REG1]], [[REG1]], -1 61; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 62; CHECK-NEXT: blr 63 %cmp = icmp ne i64 %Z, -32767 64 %conv1 = zext i1 %cmp to i64 65 %add = add nsw i64 %conv1, %X 66 ret i64 %add 67} 68 69define i64 @addze6(i64 %X, i64 %Z) { 70; CHECK-LABEL: addze6: 71; CHECK: # %bb.0: 72; CHECK-NEXT: addi [[REG1:r[0-9]+]], [[REG1]], 32767 73; CHECK-NEXT: subfic [[REG1]], [[REG1]], 0 74; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]] 75; CHECK-NEXT: blr 76 %cmp = icmp eq i64 %Z, -32767 77 %conv1 = zext i1 %cmp to i64 78 %add = add nsw i64 %conv1, %X 79 ret i64 %add 80} 81 82; element is out of range 83define i64 @test1(i64 %X, i64 %Z) { 84; CHECK-LABEL: test1: 85; CHECK: # %bb.0: 86; CHECK-NEXT: li [[REG1:r[0-9]+]], -32768 87; CHECK-NEXT: xor [[REG2:r[0-9]+]], [[REG2]], [[REG1]] 88; CHECK-NEXT: addic [[REG1]], [[REG2]], -1 89; CHECK-NEXT: subfe [[REG2]], [[REG1]], [[REG2]] 90; CHECK-NEXT: add [[REG3:r[0-9]+]], [[REG2]], [[REG3]] 91; CHECK-NEXT: blr 92 %cmp = icmp ne i64 %Z, -32768 93 %conv1 = zext i1 %cmp to i64 94 %add = add nsw i64 %conv1, %X 95 ret i64 %add 96} 97 98define i64 @test2(i64 %X, i64 %Z) { 99; CHECK-LABEL: test2: 100; CHECK: # %bb.0: 101; CHECK-NEXT: li [[REG1:r[0-9]+]], -32768 102; CHECK-NEXT: xor [[REG2:r[0-9]+]], [[REG2]], [[REG1]] 103; CHECK-NEXT: cntlzd [[REG2]], [[REG2]] 104; CHECK-NEXT: rldicl [[REG2]], [[REG2]], 58, 63 105; CHECK-NEXT: add [[REG3:r[0-9]+]], [[REG2]], [[REG3]] 106; CHECK-NEXT: blr 107 %cmp = icmp eq i64 %Z, -32768 108 %conv1 = zext i1 %cmp to i64 109 %add = add nsw i64 %conv1, %X 110 ret i64 %add 111} 112 113define i64 @test3(i64 %X, i64 %Z) { 114; CHECK-LABEL: test3: 115; CHECK: # %bb.0: 116; CHECK-NEXT: li [[REG1:r[0-9]+]], 0 117; CHECK-NEXT: ori [[REG1]], [[REG1]], 32769 118; CHECK-NEXT: xor [[REG2:r[0-9]+]], [[REG2]], [[REG1]] 119; CHECK-NEXT: addic [[REG1]], [[REG2]], -1 120; CHECK-NEXT: subfe [[REG2]], [[REG1]], [[REG2]] 121; CHECK-NEXT: add [[REG3:r[0-9]+]], [[REG2]], [[REG3]] 122; CHECK-NEXT: blr 123 %cmp = icmp ne i64 %Z, 32769 124 %conv1 = zext i1 %cmp to i64 125 %add = add nsw i64 %conv1, %X 126 ret i64 %add 127} 128 129define i64 @test4(i64 %X, i64 %Z) { 130; CHECK-LABEL: test4: 131; CHECK: # %bb.0: 132; CHECK-NEXT: li [[REG1:r[0-9]+]], 0 133; CHECK-NEXT: ori [[REG1]], [[REG1]], 32769 134; CHECK-NEXT: xor [[REG2:r[0-9]+]], [[REG2]], [[REG1]] 135; CHECK-NEXT: cntlzd [[REG2]], [[REG2]] 136; CHECK-NEXT: rldicl [[REG2]], [[REG2]], 58, 63 137; CHECK-NEXT: add [[REG3:r[0-9]+]], [[REG2]], [[REG3]] 138; CHECK-NEXT: blr 139 %cmp = icmp eq i64 %Z, 32769 140 %conv1 = zext i1 %cmp to i64 141 %add = add nsw i64 %conv1, %X 142 ret i64 %add 143} 144 145; comparison of two registers 146define i64 @test5(i64 %X, i64 %Y, i64 %Z) { 147; CHECK-LABEL: test5: 148; CHECK: # %bb.0: 149; CHECK-NEXT: xor [[REG2:r[0-9]+]], [[REG2]], [[REG1:r[0-9]+]] 150; CHECK-NEXT: addic [[REG1]], [[REG2]], -1 151; CHECK-NEXT: subfe [[REG2]], [[REG1]], [[REG2]] 152; CHECK-NEXT: add [[REG3:r[0-9]+]], [[REG2]], [[REG3]] 153; CHECK-NEXT: blr 154 %cmp = icmp ne i64 %Y, %Z 155 %conv1 = zext i1 %cmp to i64 156 %add = add nsw i64 %conv1, %X 157 ret i64 %add 158} 159 160define i64 @test6(i64 %X, i64 %Y, i64 %Z) { 161; CHECK-LABEL: test6: 162; CHECK: # %bb.0: 163; CHECK-NEXT: xor [[REG2:r[0-9]+]], [[REG2]], [[REG1:r[0-9]+]] 164; CHECK-NEXT: cntlzd [[REG2]], [[REG2]] 165; CHECK-NEXT: rldicl [[REG2]], [[REG2]], 58, 63 166; CHECK-NEXT: add [[REG3:r[0-9]+]], [[REG2]], [[REG3]] 167; CHECK-NEXT: blr 168 %cmp = icmp eq i64 %Y, %Z 169 %conv1 = zext i1 %cmp to i64 170 %add = add nsw i64 %conv1, %X 171 ret i64 %add 172} 173