1; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_20 -fp-contract=fast -verify-machineinstrs | FileCheck %s 2; RUN: %if ptxas %{ llc < %s -mtriple=nvptx64 -mcpu=sm_20 -fp-contract=fast -verify-machineinstrs | %ptxas-verify %} 3 4declare float @dummy_f32(float, float) #0 5declare double @dummy_f64(double, double) #0 6 7define ptx_device float @t1_f32(float %x, float %y, float %z) { 8; CHECK: fma.rn.f32 %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}; 9; CHECK: ret; 10 %a = fmul float %x, %y 11 %b = fadd float %a, %z 12 ret float %b 13} 14 15define ptx_device float @t2_f32(float %x, float %y, float %z, float %w) { 16; CHECK: fma.rn.f32 %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}; 17; CHECK: fma.rn.f32 %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}; 18; CHECK: ret; 19 %a = fmul float %x, %y 20 %b = fadd float %a, %z 21 %c = fadd float %a, %w 22 %d = call float @dummy_f32(float %b, float %c) 23 ret float %d 24} 25 26define ptx_device double @t1_f64(double %x, double %y, double %z) { 27; CHECK: fma.rn.f64 %fd{{[0-9]+}}, %fd{{[0-9]+}}, %fd{{[0-9]+}}, %fd{{[0-9]+}}; 28; CHECK: ret; 29 %a = fmul double %x, %y 30 %b = fadd double %a, %z 31 ret double %b 32} 33 34define ptx_device double @t2_f64(double %x, double %y, double %z, double %w) { 35; CHECK: fma.rn.f64 %fd{{[0-9]+}}, %fd{{[0-9]+}}, %fd{{[0-9]+}}, %fd{{[0-9]+}}; 36; CHECK: fma.rn.f64 %fd{{[0-9]+}}, %fd{{[0-9]+}}, %fd{{[0-9]+}}, %fd{{[0-9]+}}; 37; CHECK: ret; 38 %a = fmul double %x, %y 39 %b = fadd double %a, %z 40 %c = fadd double %a, %w 41 %d = call double @dummy_f64(double %b, double %c) 42 ret double %d 43} 44 45define ptx_device float @f32_iir(float %x) { 46; CHECK: fma.rn.f32 %f{{[0-9]+}}, 0f52E8D4A5, 0f4A52FC54, %f{{[0-9]+}}; 47; CHECK: ret; 48 %r = call float @llvm.fma.f32(float 499999997952.0, float 3456789.0, float %x) 49 ret float %r 50} 51 52define ptx_device float @f32_iii(float %x) { 53; CHECK: mov.f32 %f{{[0-9]+}}, 0f41200000; 54; CHECK: ret; 55 %r = call float @llvm.fma.f32(float 2.0, float 3.0, float 4.0) 56 ret float %r 57} 58