xref: /llvm-project/llvm/test/CodeGen/NVPTX/dag-cse.ll (revision b279f6b098d3849f7f1c1f539b108307d5f8ae2d)
1; RUN: llc < %s -mtriple=nvptx64 | FileCheck %s
2
3%st = type { i8, i8, i16 }
4
5@a = internal addrspace(1) global %st zeroinitializer, align 8
6@b = internal addrspace(1) global i32 0, align 8
7@c = internal addrspace(1) global i32 0, align 8
8
9; Verify that loads with different memory types are not subject to CSE
10; once they are promoted to the same type.
11;
12; CHECK: ld.global.v2.u8  {%[[B1:rs[0-9]+]], %[[B2:rs[0-9]+]]}, [a];
13; CHECK: st.global.v2.u8  [b], {%[[B1]], %[[B2]]};
14;
15; CHECK: ld.global.u32 %[[C:r[0-9]+]], [a];
16; CHECK: st.global.u32 [c], %[[C]];
17
18define void @test1() #0 {
19  %1 = load <2 x i8>, ptr addrspace(1) @a, align 8
20  store <2 x i8> %1, ptr addrspace(1) @b, align 8
21  %2 = load <2 x i16>, ptr addrspace(1) @a, align 8
22  store <2 x i16> %2, ptr addrspace(1) @c, align 8
23  ret void
24}
25