xref: /llvm-project/llvm/test/CodeGen/NVPTX/convert-int-sm20.ll (revision b279f6b098d3849f7f1c1f539b108307d5f8ae2d)
1; RUN: llc < %s -mtriple=nvptx -mcpu=sm_20 | FileCheck %s
2; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_20 | FileCheck %s
3; RUN: %if ptxas && !ptxas-12.0 %{ llc < %s -mtriple=nvptx -mcpu=sm_20 | %ptxas-verify %}
4; RUN: %if ptxas %{ llc < %s -mtriple=nvptx64 -mcpu=sm_20 | %ptxas-verify %}
5
6
7;; Integer conversions happen inplicitly by loading/storing the proper types
8
9
10; i16
11
12define i16 @cvt_i16_i32(i32 %x) {
13; CHECK: ld.param.u16 %r[[R0:[0-9]+]], [cvt_i16_i32_param_{{[0-9]+}}]
14; CHECK: st.param.b32 [func_retval{{[0-9]+}}], %r[[R0]]
15; CHECK: ret
16  %a = trunc i32 %x to i16
17  ret i16 %a
18}
19
20define i16 @cvt_i16_i64(i64 %x) {
21; CHECK: ld.param.u16 %r[[R0:[0-9]+]], [cvt_i16_i64_param_{{[0-9]+}}]
22; CHECK: st.param.b32 [func_retval{{[0-9]+}}], %r[[R0]]
23; CHECK: ret
24  %a = trunc i64 %x to i16
25  ret i16 %a
26}
27
28
29
30; i32
31
32define i32 @cvt_i32_i16(i16 %x) {
33; CHECK: ld.param.u16 %r[[R0:[0-9]+]], [cvt_i32_i16_param_{{[0-9]+}}]
34; CHECK: st.param.b32 [func_retval{{[0-9]+}}], %r[[R0]]
35; CHECK: ret
36  %a = zext i16 %x to i32
37  ret i32 %a
38}
39
40define i32 @cvt_i32_i64(i64 %x) {
41; CHECK: ld.param.u32 %r[[R0:[0-9]+]], [cvt_i32_i64_param_{{[0-9]+}}]
42; CHECK: st.param.b32 [func_retval{{[0-9]+}}], %r[[R0]]
43; CHECK: ret
44  %a = trunc i64 %x to i32
45  ret i32 %a
46}
47
48
49
50; i64
51
52define i64 @cvt_i64_i16(i16 %x) {
53; CHECK: ld.param.u16 %rd[[R0:[0-9]+]], [cvt_i64_i16_param_{{[0-9]+}}]
54; CHECK: st.param.b64 [func_retval{{[0-9]+}}], %rd[[R0]]
55; CHECK: ret
56  %a = zext i16 %x to i64
57  ret i64 %a
58}
59
60define i64 @cvt_i64_i32(i32 %x) {
61; CHECK: ld.param.u32 %rd[[R0:[0-9]+]], [cvt_i64_i32_param_{{[0-9]+}}]
62; CHECK: st.param.b64 [func_retval{{[0-9]+}}], %rd[[R0]]
63; CHECK: ret
64  %a = zext i32 %x to i64
65  ret i64 %a
66}
67