xref: /llvm-project/llvm/test/CodeGen/NVPTX/bug52623.ll (revision b279f6b098d3849f7f1c1f539b108307d5f8ae2d)
1; RUN: llc < %s -mtriple=nvptx64 -verify-machineinstrs
2; RUN: %if ptxas %{ llc < %s -mtriple=nvptx64 | %ptxas-verify %}
3
4; Check that llc will not crash even when first MBB doesn't contain
5; any instruction.
6
7target datalayout = "e-i64:64-i128:128-v16:16-v32:32-n16:32:64"
8target triple = "nvptx64"
9
10%printf_args.0.8 = type { ptr }
11
12define internal i32 @__kmpc_get_hardware_thread_id_in_block(i1 %0) {
13  %2 = alloca %printf_args.0.8, i32 0, align 8
14  br i1 true, label %._crit_edge1, label %._crit_edge
15
16._crit_edge:                                      ; preds = %1, %._crit_edge
17  %3 = call i32 null(ptr null, ptr %2)
18  br i1 %0, label %._crit_edge, label %._crit_edge1
19
20._crit_edge1:                                     ; preds = %._crit_edge, %1
21  ret i32 0
22
23; uselistorder directives
24  uselistorder label %._crit_edge, { 1, 0 }
25}
26