1; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_20 | FileCheck %s 2; RUN: %if ptxas %{ llc < %s -mtriple=nvptx64 -mcpu=sm_20 | %ptxas-verify %} 3 4 5; CHECK: bfe0 6define i32 @bfe0(i32 %a) { 7; CHECK: bfe.u32 %r{{[0-9]+}}, %r{{[0-9]+}}, 4, 4 8; CHECK-NOT: shr 9; CHECK-NOT: and 10 %val0 = ashr i32 %a, 4 11 %val1 = and i32 %val0, 15 12 ret i32 %val1 13} 14 15; CHECK: bfe1 16define i32 @bfe1(i32 %a) { 17; CHECK: bfe.u32 %r{{[0-9]+}}, %r{{[0-9]+}}, 3, 3 18; CHECK-NOT: shr 19; CHECK-NOT: and 20 %val0 = ashr i32 %a, 3 21 %val1 = and i32 %val0, 7 22 ret i32 %val1 23} 24 25; CHECK: bfe2 26define i32 @bfe2(i32 %a) { 27; CHECK: bfe.u32 %r{{[0-9]+}}, %r{{[0-9]+}}, 5, 3 28; CHECK-NOT: shr 29; CHECK-NOT: and 30 %val0 = ashr i32 %a, 5 31 %val1 = and i32 %val0, 7 32 ret i32 %val1 33} 34 35; CHECK-LABEL: no_bfe_on_32bit_overflow 36define i32 @no_bfe_on_32bit_overflow(i32 %a) { 37; CHECK-NOT: bfe.u32 %r{{[0-9]+}}, %r{{[0-9]+}}, 31, 4 38 %val0 = ashr i32 %a, 31 39 %val1 = and i32 %val0, 15 40 ret i32 %val1 41} 42 43; CHECK-LABEL: no_bfe_on_32bit_overflow_shr_and_pair 44define i32 @no_bfe_on_32bit_overflow_shr_and_pair(i32 %a) { 45; CHECK: shr.s32 %r{{[0-9]+}}, %r{{[0-9]+}}, 31 46; CHECK: and.b32 %r{{[0-9]+}}, %r{{[0-9]+}}, 15 47 %val0 = ashr i32 %a, 31 48 %val1 = and i32 %val0, 15 49 ret i32 %val1 50} 51 52; CHECK-LABEL: no_bfe_on_64bit_overflow 53define i64 @no_bfe_on_64bit_overflow(i64 %a) { 54; CHECK-NOT: bfe.u64 %rd{{[0-9]+}}, %rd{{[0-9]+}}, 63, 3 55 %val0 = ashr i64 %a, 63 56 %val1 = and i64 %val0, 7 57 ret i64 %val1 58} 59 60; CHECK-LABEL: no_bfe_on_64bit_overflow_shr_and_pair 61define i64 @no_bfe_on_64bit_overflow_shr_and_pair(i64 %a) { 62; CHECK: shr.s64 %rd{{[0-9]+}}, %rd{{[0-9]+}}, 63 63; CHECK: and.b64 %rd{{[0-9]+}}, %rd{{[0-9]+}}, 7 64 %val0 = ashr i64 %a, 63 65 %val1 = and i64 %val0, 7 66 ret i64 %val1 67} 68