xref: /llvm-project/llvm/test/CodeGen/NVPTX/arithmetic-fp-sm20.ll (revision b279f6b098d3849f7f1c1f539b108307d5f8ae2d)
1; RUN: llc < %s -mtriple=nvptx -mcpu=sm_20 -fp-contract=fast | FileCheck %s
2; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_20 -fp-contract=fast | FileCheck %s
3; RUN: %if ptxas && !ptxas-12.0 %{ llc < %s -mtriple=nvptx -mcpu=sm_20 -fp-contract=fast | %ptxas-verify %}
4; RUN: %if ptxas %{ llc < %s -mtriple=nvptx64 -mcpu=sm_20 -fp-contract=fast | %ptxas-verify %}
5
6;; These tests should run for all targets
7
8;;===-- Basic instruction selection tests ---------------------------------===;;
9
10
11;;; f64
12
13define double @fadd_f64(double %a, double %b) {
14; CHECK: add.f64 %fd{{[0-9]+}}, %fd{{[0-9]+}}, %fd{{[0-9]+}}
15; CHECK: ret
16  %ret = fadd double %a, %b
17  ret double %ret
18}
19
20define double @fsub_f64(double %a, double %b) {
21; CHECK: sub.f64 %fd{{[0-9]+}}, %fd{{[0-9]+}}, %fd{{[0-9]+}}
22; CHECK: ret
23  %ret = fsub double %a, %b
24  ret double %ret
25}
26
27define double @fmul_f64(double %a, double %b) {
28; CHECK: mul.f64 %fd{{[0-9]+}}, %fd{{[0-9]+}}, %fd{{[0-9]+}}
29; CHECK: ret
30  %ret = fmul double %a, %b
31  ret double %ret
32}
33
34define double @fdiv_f64(double %a, double %b) {
35; CHECK: div.rn.f64 %fd{{[0-9]+}}, %fd{{[0-9]+}}, %fd{{[0-9]+}}
36; CHECK: ret
37  %ret = fdiv double %a, %b
38  ret double %ret
39}
40
41;; PTX does not have a floating-point rem instruction
42
43
44;;; f32
45
46define float @fadd_f32(float %a, float %b) {
47; CHECK: add.f32 %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}
48; CHECK: ret
49  %ret = fadd float %a, %b
50  ret float %ret
51}
52
53define float @fsub_f32(float %a, float %b) {
54; CHECK: sub.f32 %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}
55; CHECK: ret
56  %ret = fsub float %a, %b
57  ret float %ret
58}
59
60define float @fmul_f32(float %a, float %b) {
61; CHECK: mul.f32 %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}
62; CHECK: ret
63  %ret = fmul float %a, %b
64  ret float %ret
65}
66
67define float @fdiv_f32(float %a, float %b) {
68; CHECK: div.rn.f32 %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}
69; CHECK: ret
70  %ret = fdiv float %a, %b
71  ret float %ret
72}
73
74;; PTX does not have a floating-point rem instruction
75