xref: /llvm-project/llvm/test/CodeGen/Mips/optimizeAndPlusShift.ll (revision e13e95bc44b0f3cd4312078ecf98889888bc0511)
1; RUN: llc < %s -mtriple=mipsel-unknown-linux-gnu | FileCheck %s --check-prefixes=MIPS32
2; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnuabi64 | FileCheck %s --check-prefixes=MIPS64
3; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnuabi64 | FileCheck %s --check-prefixes=MIPS64
4
5define i32 @shl_32(i32 %a, i32 %b) {
6; MIPS32-LABLE:   shl_32:
7; MIPS32:	  # %bb.0:
8; MIPS32-NEXT:    jr	$ra
9; MIPS32-NEXT:    sllv	$2, $4, $5
10; MIPS64-LABLE:   shl_32:
11; MIPS64:	  # %bb.0:
12; MIPS64-NEXT:    sll   $1, $5, 0
13; MIPS64-NEXT:    sll   $2, $4, 0
14; MIPS64-NEXT:    jr	$ra
15; MIPS64-NEXT:    sllv	$2, $2, $1
16  %_1 = and i32 %b, 31
17  %_0 = shl i32 %a, %_1
18  ret i32 %_0
19}
20
21define i32 @lshr_32(i32 %a, i32 %b) {
22; MIPS32-LABLE:   lshr_32:
23; MIPS32:	  # %bb.0:
24; MIPS32-NEXT:    jr	$ra
25; MIPS32-NEXT:    srlv	$2, $4, $5
26; MIPS64-LABLE:   lshr_32:
27; MIPS64:	  # %bb.0:
28; MIPS64-NEXT:    sll   $1, $5, 0
29; MIPS64-NEXT:    sll   $2, $4, 0
30; MIPS64-NEXT:    jr	$ra
31; MIPS64-NEXT:    srlv	$2, $2, $1
32  %_1 = and i32 %b, 31
33  %_0 = lshr i32 %a, %_1
34  ret i32 %_0
35}
36
37define i32 @ashr_32(i32 %a, i32 %b) {
38; MIPS32-LABLE:   ashr_32:
39; MIPS32:	  # %bb.0:
40; MIPS32-NEXT:    jr	$ra
41; MIPS32-NEXT:    srav	$2, $4, $5
42; MIPS64-LABLE:   ashr_32:
43; MIPS64:	  # %bb.0:
44; MIPS64-NEXT:    sll   $1, $5, 0
45; MIPS64-NEXT:    sll   $2, $4, 0
46; MIPS64-NEXT:    jr	$ra
47; MIPS64-NEXT:    srav	$2, $2, $1
48  %_1 = and i32 %b, 31
49  %_0 = ashr i32 %a, %_1
50  ret i32 %_0
51}
52
53define i64 @shl_64(i64 %a, i64 %b) {
54; MIPS64-LABLE:   shl_64:
55; MIPS64:	  # %bb.0:
56; MIPS64-NEXT:    sll   $1, $5, 0
57; MIPS64-NEXT:    jr	$ra
58; MIPS64-NEXT:    dsllv	$2, $4, $1
59  %_1 = and i64 %b, 63
60  %_0 = shl i64 %a, %_1
61  ret i64 %_0
62}
63
64define i64 @lshr_64(i64 %a, i64 %b) {
65; MIPS64-LABLE:   lshr_64:
66; MIPS64:	  # %bb.0:
67; MIPS64-NEXT:    sll   $1, $5, 0
68; MIPS64-NEXT:    jr	$ra
69; MIPS64-NEXT:    dsrlv	$2, $4, $1
70  %_1 = and i64 %b, 63
71  %_0 = lshr i64 %a, %_1
72  ret i64 %_0
73}
74
75define i64 @ashr_64(i64 %a, i64 %b) {
76; MIPS64-LABLE:   ashr_64:
77; MIPS64:	  # %bb.0:
78; MIPS64-NEXT:    sll   $1, $5, 0
79; MIPS64-NEXT:    jr	$ra
80; MIPS64-NEXT:    dsrav	$2, $4, $1
81  %_1 = and i64 %b, 63
82  %_0 = ashr i64 %a, %_1
83  ret i64 %_0
84}
85