1; Test the MSA intrinsics that are encoded with the I5 instruction format and 2; are loads or stores. 3 4; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s 5; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s 6 7@llvm_mips_ld_b_ARG = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 8@llvm_mips_ld_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 9 10define void @llvm_mips_ld_b_test() nounwind { 11entry: 12 %0 = tail call <16 x i8> @llvm.mips.ld.b(ptr @llvm_mips_ld_b_ARG, i32 16) 13 store <16 x i8> %0, ptr @llvm_mips_ld_b_RES 14 ret void 15} 16 17declare <16 x i8> @llvm.mips.ld.b(ptr, i32) nounwind 18 19; CHECK: llvm_mips_ld_b_test: 20; CHECK: ld.b [[R1:\$w[0-9]+]], 16( 21; CHECK: st.b 22; CHECK: .size llvm_mips_ld_b_test 23; 24 25define void @llvm_mips_ld_b_unaligned_test() nounwind { 26entry: 27 %0 = tail call <16 x i8> @llvm.mips.ld.b(ptr @llvm_mips_ld_b_ARG, i32 9) 28 store <16 x i8> %0, ptr @llvm_mips_ld_b_RES 29 ret void 30} 31 32; CHECK: llvm_mips_ld_b_unaligned_test: 33; CHECK: ld.b [[R1:\$w[0-9]+]], 9( 34; CHECK: st.b 35; CHECK: .size llvm_mips_ld_b_unaligned_test 36; 37 38define void @llvm_mips_ld_b_valid_range_tests() nounwind { 39entry: 40 %0 = tail call <16 x i8> @llvm.mips.ld.b(ptr @llvm_mips_ld_b_ARG, i32 -512) 41 store <16 x i8> %0, ptr @llvm_mips_ld_b_RES 42 %1 = tail call <16 x i8> @llvm.mips.ld.b(ptr @llvm_mips_ld_b_ARG, i32 511) 43 store <16 x i8> %1, ptr @llvm_mips_ld_b_RES 44 ret void 45} 46 47; CHECK: llvm_mips_ld_b_valid_range_tests: 48; CHECK: ld.b [[R1:\$w[0-9]+]], -512( 49; CHECK: st.b 50; CHECK: ld.b [[R1:\$w[0-9]+]], 511( 51; CHECK: st.b 52; CHECK: .size llvm_mips_ld_b_valid_range_tests 53; 54 55define void @llvm_mips_ld_b_invalid_range_tests() nounwind { 56entry: 57 %0 = tail call <16 x i8> @llvm.mips.ld.b(ptr @llvm_mips_ld_b_ARG, i32 -513) 58 store <16 x i8> %0, ptr @llvm_mips_ld_b_RES 59 %1 = tail call <16 x i8> @llvm.mips.ld.b(ptr @llvm_mips_ld_b_ARG, i32 512) 60 store <16 x i8> %1, ptr @llvm_mips_ld_b_RES 61 ret void 62} 63 64; CHECK: llvm_mips_ld_b_invalid_range_tests: 65; CHECK: addiu $3, $2, -513 66; CHECK: ld.b [[R1:\$w[0-9]+]], 0( 67; CHECK: st.b 68; CHECK: addiu $2, $2, 512 69; CHECK: ld.b [[R1:\$w[0-9]+]], 0( 70; CHECK: st.b 71; CHECK: .size llvm_mips_ld_b_invalid_range_tests 72; 73 74@llvm_mips_ld_h_ARG = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 75@llvm_mips_ld_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 76 77define void @llvm_mips_ld_h_test() nounwind { 78entry: 79 %0 = tail call <8 x i16> @llvm.mips.ld.h(ptr @llvm_mips_ld_h_ARG, i32 16) 80 store <8 x i16> %0, ptr @llvm_mips_ld_h_RES 81 ret void 82} 83 84declare <8 x i16> @llvm.mips.ld.h(ptr, i32) nounwind 85 86; CHECK: llvm_mips_ld_h_test: 87; CHECK: ld.h [[R1:\$w[0-9]+]], 16( 88; CHECK: st.h 89; CHECK: .size llvm_mips_ld_h_test 90; 91 92define void @llvm_mips_ld_h_unaligned_test() nounwind { 93entry: 94 %0 = tail call <8 x i16> @llvm.mips.ld.h(ptr @llvm_mips_ld_h_ARG, i32 9) 95 store <8 x i16> %0, ptr @llvm_mips_ld_h_RES 96 ret void 97} 98 99; CHECK: llvm_mips_ld_h_unaligned_test: 100; CHECK: addiu $2, $2, 9 101; CHECK: ld.h [[R1:\$w[0-9]+]], 0($2) 102; CHECK: st.h 103; CHECK: .size llvm_mips_ld_h_unaligned_test 104; 105 106define void @llvm_mips_ld_h_valid_range_tests() nounwind { 107entry: 108 %0 = tail call <8 x i16> @llvm.mips.ld.h(ptr @llvm_mips_ld_h_ARG, i32 -1024) 109 store <8 x i16> %0, ptr @llvm_mips_ld_h_RES 110 %1 = tail call <8 x i16> @llvm.mips.ld.h(ptr @llvm_mips_ld_h_ARG, i32 1022) 111 store <8 x i16> %1, ptr @llvm_mips_ld_h_RES 112 ret void 113} 114 115; CHECK: llvm_mips_ld_h_valid_range_tests: 116; CHECK: ld.h [[R1:\$w[0-9]+]], -1024( 117; CHECK: st.h 118; CHECK: ld.h [[R1:\$w[0-9]+]], 1022( 119; CHECK: st.h 120; CHECK: .size llvm_mips_ld_h_valid_range_tests 121; 122 123define void @llvm_mips_ld_h_invalid_range_tests() nounwind { 124entry: 125 %0 = tail call <8 x i16> @llvm.mips.ld.h(ptr @llvm_mips_ld_h_ARG, i32 -1026) 126 store <8 x i16> %0, ptr @llvm_mips_ld_h_RES 127 %1 = tail call <8 x i16> @llvm.mips.ld.h(ptr @llvm_mips_ld_h_ARG, i32 1024) 128 store <8 x i16> %1, ptr @llvm_mips_ld_h_RES 129 ret void 130} 131 132; CHECK: llvm_mips_ld_h_invalid_range_tests: 133; CHECK: addiu $3, $2, -1026 134; CHECK: ld.h [[R1:\$w[0-9]+]], 0( 135; CHECK: st.h 136; CHECK: addiu $2, $2, 1024 137; CHECK: ld.h [[R1:\$w[0-9]+]], 0( 138; CHECK: st.h 139; CHECK: .size llvm_mips_ld_h_invalid_range_tests 140; 141 142@llvm_mips_ld_w_ARG = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 143@llvm_mips_ld_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 144 145define void @llvm_mips_ld_w_test() nounwind { 146entry: 147 %0 = tail call <4 x i32> @llvm.mips.ld.w(ptr @llvm_mips_ld_w_ARG, i32 16) 148 store <4 x i32> %0, ptr @llvm_mips_ld_w_RES 149 ret void 150} 151 152declare <4 x i32> @llvm.mips.ld.w(ptr, i32) nounwind 153 154; CHECK: llvm_mips_ld_w_test: 155; CHECK: ld.w [[R1:\$w[0-9]+]], 16( 156; CHECK: st.w 157; CHECK: .size llvm_mips_ld_w_test 158; 159@llvm_mips_ld_d_ARG = global <2 x i64> <i64 0, i64 1>, align 16 160@llvm_mips_ld_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 161 162define void @llvm_mips_ld_w_unaligned_test() nounwind { 163entry: 164 %0 = tail call <4 x i32> @llvm.mips.ld.w(ptr @llvm_mips_ld_w_ARG, i32 9) 165 store <4 x i32> %0, ptr @llvm_mips_ld_w_RES 166 ret void 167} 168 169; CHECK: llvm_mips_ld_w_unaligned_test: 170; CHECK: addiu $2, $2, 9 171; CHECK: ld.w [[R1:\$w[0-9]+]], 0($2) 172; CHECK: st.w 173; CHECK: .size llvm_mips_ld_w_unaligned_test 174; 175 176define void @llvm_mips_ld_w_valid_range_tests() nounwind { 177entry: 178 %0 = tail call <4 x i32> @llvm.mips.ld.w(ptr @llvm_mips_ld_w_ARG, i32 -2048) 179 store <4 x i32> %0, ptr @llvm_mips_ld_w_RES 180 %1 = tail call <4 x i32> @llvm.mips.ld.w(ptr @llvm_mips_ld_w_ARG, i32 2044) 181 store <4 x i32> %1, ptr @llvm_mips_ld_w_RES 182 ret void 183} 184 185; CHECK: llvm_mips_ld_w_valid_range_tests: 186; CHECK: ld.w [[R1:\$w[0-9]+]], -2048( 187; CHECK: st.w 188; CHECK: ld.w [[R1:\$w[0-9]+]], 2044( 189; CHECK: st.w 190; CHECK: .size llvm_mips_ld_w_valid_range_tests 191; 192 193define void @llvm_mips_ld_w_invalid_range_tests() nounwind { 194entry: 195 %0 = tail call <4 x i32> @llvm.mips.ld.w(ptr @llvm_mips_ld_w_ARG, i32 -2052) 196 store <4 x i32> %0, ptr @llvm_mips_ld_w_RES 197 %1 = tail call <4 x i32> @llvm.mips.ld.w(ptr @llvm_mips_ld_w_ARG, i32 2048) 198 store <4 x i32> %1, ptr @llvm_mips_ld_w_RES 199 ret void 200} 201 202; CHECK: llvm_mips_ld_w_invalid_range_tests: 203; CHECK: addiu $3, $2, -2052 204; CHECK: ld.w [[R1:\$w[0-9]+]], 0( 205; CHECK: st.w 206; CHECK: addiu $2, $2, 2048 207; CHECK: ld.w [[R1:\$w[0-9]+]], 0( 208; CHECK: st.w 209; CHECK: .size llvm_mips_ld_w_invalid_range_tests 210; 211 212define void @llvm_mips_ld_d_test() nounwind { 213entry: 214 %0 = tail call <2 x i64> @llvm.mips.ld.d(ptr @llvm_mips_ld_d_ARG, i32 16) 215 store <2 x i64> %0, ptr @llvm_mips_ld_d_RES 216 ret void 217} 218 219declare <2 x i64> @llvm.mips.ld.d(ptr, i32) nounwind 220 221; CHECK: llvm_mips_ld_d_test: 222; CHECK: ld.d [[R1:\$w[0-9]+]], 16( 223; CHECK: st.d 224; CHECK: .size llvm_mips_ld_d_test 225; 226 227define void @llvm_mips_ld_d_unaligned_test() nounwind { 228entry: 229 %0 = tail call <2 x i64> @llvm.mips.ld.d(ptr @llvm_mips_ld_d_ARG, i32 9) 230 store <2 x i64> %0, ptr @llvm_mips_ld_d_RES 231 ret void 232} 233 234; CHECK: llvm_mips_ld_d_unaligned_test: 235; CHECK: addiu $2, $2, 9 236; CHECK: ld.d [[R1:\$w[0-9]+]], 0($2) 237; CHECK: st.d 238; CHECK: .size llvm_mips_ld_d_unaligned_test 239; 240 241define void @llvm_mips_ld_d_valid_range_tests() nounwind { 242entry: 243 %0 = tail call <2 x i64> @llvm.mips.ld.d(ptr @llvm_mips_ld_d_ARG, i32 -4096) 244 store <2 x i64> %0, ptr @llvm_mips_ld_d_RES 245 %1 = tail call <2 x i64> @llvm.mips.ld.d(ptr @llvm_mips_ld_d_ARG, i32 4088) 246 store <2 x i64> %1, ptr @llvm_mips_ld_d_RES 247 ret void 248} 249 250; CHECK: llvm_mips_ld_d_valid_range_tests: 251; CHECK: ld.d [[R1:\$w[0-9]+]], -4096( 252; CHECK: st.d 253; CHECK: ld.d [[R1:\$w[0-9]+]], 4088( 254; CHECK: st.d 255; CHECK: .size llvm_mips_ld_d_valid_range_tests 256; 257 258define void @llvm_mips_ld_d_invalid_range_tests() nounwind { 259entry: 260 %0 = tail call <2 x i64> @llvm.mips.ld.d(ptr @llvm_mips_ld_d_ARG, i32 -4104) 261 store <2 x i64> %0, ptr @llvm_mips_ld_d_RES 262 %1 = tail call <2 x i64> @llvm.mips.ld.d(ptr @llvm_mips_ld_d_ARG, i32 4096) 263 store <2 x i64> %1, ptr @llvm_mips_ld_d_RES 264 ret void 265} 266 267; CHECK: llvm_mips_ld_d_invalid_range_tests: 268; CHECK: addiu $3, $2, -4104 269; CHECK: ld.d [[R1:\$w[0-9]+]], 0( 270; CHECK: st.d 271; CHECK: addiu $2, $2, 4096 272; CHECK: ld.d [[R1:\$w[0-9]+]], 0( 273; CHECK: st.d 274; CHECK: .size llvm_mips_ld_d_invalid_range_tests 275; 276 277 278 279@llvm_mips_st_b_ARG = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 280@llvm_mips_st_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 281 282define void @llvm_mips_st_b_test() nounwind { 283entry: 284 %0 = load <16 x i8>, ptr @llvm_mips_st_b_ARG 285 tail call void @llvm.mips.st.b(<16 x i8> %0, ptr @llvm_mips_st_b_RES, i32 16) 286 ret void 287} 288 289declare void @llvm.mips.st.b(<16 x i8>, ptr, i32) nounwind 290 291; CHECK: llvm_mips_st_b_test: 292; CHECK: ld.b 293; CHECK: st.b [[R1:\$w[0-9]+]], 16( 294; CHECK: .size llvm_mips_st_b_test 295; 296 297define void @llvm_mips_st_b_unaligned_test() nounwind { 298entry: 299 %0 = load <16 x i8>, ptr @llvm_mips_st_b_ARG 300 tail call void @llvm.mips.st.b(<16 x i8> %0, ptr @llvm_mips_st_b_RES, i32 9) 301 ret void 302} 303 304; CHECK: llvm_mips_st_b_unaligned_test: 305; CHECK: ld.b 306; CHECK: st.b [[R1:\$w[0-9]+]], 9( 307; CHECK: .size llvm_mips_st_b_unaligned_test 308; 309 310define void @llvm_mips_st_b_valid_range_tests() nounwind { 311entry: 312 %0 = load <16 x i8>, ptr @llvm_mips_st_b_ARG 313 tail call void @llvm.mips.st.b(<16 x i8> %0, ptr @llvm_mips_st_b_RES, i32 -512) 314 tail call void @llvm.mips.st.b(<16 x i8> %0, ptr @llvm_mips_st_b_RES, i32 511) 315 ret void 316} 317 318; CHECK: llvm_mips_st_b_valid_range_tests: 319; CHECK: ld.b 320; CHECK-DAG: st.b [[R1:\$w[0-9]+]], -512( 321; CHECK-DAG: st.b [[R1:\$w[0-9]+]], 511( 322; CHECK: .size llvm_mips_st_b_valid_range_tests 323; 324 325define void @llvm_mips_st_b_invalid_range_tests() nounwind { 326entry: 327 %0 = load <16 x i8>, ptr @llvm_mips_st_b_ARG 328 tail call void @llvm.mips.st.b(<16 x i8> %0, ptr @llvm_mips_st_b_RES, i32 -513) 329 tail call void @llvm.mips.st.b(<16 x i8> %0, ptr @llvm_mips_st_b_RES, i32 512) 330 ret void 331} 332 333; CHECK: llvm_mips_st_b_invalid_range_tests: 334; CHECK: addiu $2, $1, 512 335; CHECK: ld.b 336; CHECK: st.b [[R1:\$w[0-9]+]], 0( 337; CHECK: addiu $1, $1, -513 338; CHECK: st.b [[R1:\$w[0-9]+]], 0( 339; CHECK: .size llvm_mips_st_b_invalid_range_tests 340; 341 342@llvm_mips_st_h_ARG = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 343@llvm_mips_st_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 344 345define void @llvm_mips_st_h_test() nounwind { 346entry: 347 %0 = load <8 x i16>, ptr @llvm_mips_st_h_ARG 348 tail call void @llvm.mips.st.h(<8 x i16> %0, ptr @llvm_mips_st_h_RES, i32 16) 349 ret void 350} 351 352declare void @llvm.mips.st.h(<8 x i16>, ptr, i32) nounwind 353 354; CHECK: llvm_mips_st_h_test: 355; CHECK: ld.h 356; CHECK: st.h [[R1:\$w[0-9]+]], 16( 357; CHECK: .size llvm_mips_st_h_test 358; 359 360define void @llvm_mips_st_h_unaligned_test() nounwind { 361entry: 362 %0 = load <8 x i16>, ptr @llvm_mips_st_h_ARG 363 tail call void @llvm.mips.st.h(<8 x i16> %0, ptr @llvm_mips_st_h_RES, i32 9) 364 ret void 365} 366 367; CHECK: llvm_mips_st_h_unaligned_test: 368; CHECK: addiu $1, $1, 9 369; CHECK: ld.h 370; CHECK: st.h [[R1:\$w[0-9]+]], 0($1) 371; CHECK: .size llvm_mips_st_h_unaligned_test 372; 373 374define void @llvm_mips_st_h_valid_range_tests() nounwind { 375entry: 376 %0 = load <8 x i16>, ptr @llvm_mips_st_h_ARG 377 tail call void @llvm.mips.st.h(<8 x i16> %0, ptr @llvm_mips_st_h_RES, i32 -1024) 378 tail call void @llvm.mips.st.h(<8 x i16> %0, ptr @llvm_mips_st_h_RES, i32 1022) 379 ret void 380} 381 382; CHECK: llvm_mips_st_h_valid_range_tests: 383; CHECK: ld.h 384; CHECK-DAG: st.h [[R1:\$w[0-9]+]], -1024( 385; CHECK-DAG: st.h [[R1:\$w[0-9]+]], 1022( 386; CHECK: .size llvm_mips_st_h_valid_range_tests 387; 388 389define void @llvm_mips_st_h_invalid_range_tests() nounwind { 390entry: 391 %0 = load <8 x i16>, ptr @llvm_mips_st_h_ARG 392 tail call void @llvm.mips.st.h(<8 x i16> %0, ptr @llvm_mips_st_h_RES, i32 -1026) 393 tail call void @llvm.mips.st.h(<8 x i16> %0, ptr @llvm_mips_st_h_RES, i32 1024) 394 ret void 395} 396 397; CHECK: llvm_mips_st_h_invalid_range_tests: 398; CHECK: addiu $2, $1, 1024 399; CHECK: ld.h 400; CHECK: st.h [[R1:\$w[0-9]+]], 0( 401; CHECK: addiu $1, $1, -1026 402; CHECK: st.h [[R1:\$w[0-9]+]], 0( 403; CHECK: .size llvm_mips_st_h_invalid_range_tests 404; 405 406@llvm_mips_st_w_ARG = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 407@llvm_mips_st_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 408 409define void @llvm_mips_st_w_test() nounwind { 410entry: 411 %0 = load <4 x i32>, ptr @llvm_mips_st_w_ARG 412 tail call void @llvm.mips.st.w(<4 x i32> %0, ptr @llvm_mips_st_w_RES, i32 16) 413 ret void 414} 415 416declare void @llvm.mips.st.w(<4 x i32>, ptr, i32) nounwind 417 418; CHECK: llvm_mips_st_w_test: 419; CHECK: ld.w 420; CHECK: st.w [[R1:\$w[0-9]+]], 16( 421; CHECK: .size llvm_mips_st_w_test 422; 423 424define void @llvm_mips_st_w_unaligned_test() nounwind { 425entry: 426 %0 = load <4 x i32>, ptr @llvm_mips_st_w_ARG 427 tail call void @llvm.mips.st.w(<4 x i32> %0, ptr @llvm_mips_st_w_RES, i32 9) 428 ret void 429} 430 431; CHECK: llvm_mips_st_w_unaligned_test: 432; CHECK: addiu $1, $1, 9 433; CHECK: ld.w 434; CHECK: st.w [[R1:\$w[0-9]+]], 0($1) 435; CHECK: .size llvm_mips_st_w_unaligned_test 436; 437 438define void @llvm_mips_st_w_valid_range_tests() nounwind { 439entry: 440 %0 = load <4 x i32>, ptr @llvm_mips_st_w_ARG 441 tail call void @llvm.mips.st.w(<4 x i32> %0, ptr @llvm_mips_st_w_RES, i32 -2048) 442 tail call void @llvm.mips.st.w(<4 x i32> %0, ptr @llvm_mips_st_w_RES, i32 2044) 443 ret void 444} 445 446; CHECK: llvm_mips_st_w_valid_range_tests: 447; CHECK: ld.w 448; CHECK-DAG: st.w [[R1:\$w[0-9]+]], -2048( 449; CHECK-DAG: st.w [[R1:\$w[0-9]+]], 2044( 450; CHECK: .size llvm_mips_st_w_valid_range_tests 451; 452 453define void @llvm_mips_st_w_invalid_range_tests() nounwind { 454entry: 455 %0 = load <4 x i32>, ptr @llvm_mips_st_w_ARG 456 tail call void @llvm.mips.st.w(<4 x i32> %0, ptr @llvm_mips_st_w_RES, i32 -2052) 457 tail call void @llvm.mips.st.w(<4 x i32> %0, ptr @llvm_mips_st_w_RES, i32 2048) 458 ret void 459} 460 461; CHECK: llvm_mips_st_w_invalid_range_tests: 462; CHECK: addiu $2, $1, 2048 463; CHECK: ld.w 464; CHECK: st.w [[R1:\$w[0-9]+]], 0( 465; CHECK: addiu $1, $1, -2052 466; CHECK: st.w [[R1:\$w[0-9]+]], 0( 467; CHECK: .size llvm_mips_st_w_invalid_range_tests 468; 469 470@llvm_mips_st_d_ARG = global <2 x i64> <i64 0, i64 1>, align 16 471@llvm_mips_st_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 472 473define void @llvm_mips_st_d_test() nounwind { 474entry: 475 %0 = load <2 x i64>, ptr @llvm_mips_st_d_ARG 476 tail call void @llvm.mips.st.d(<2 x i64> %0, ptr @llvm_mips_st_d_RES, i32 16) 477 ret void 478} 479 480declare void @llvm.mips.st.d(<2 x i64>, ptr, i32) nounwind 481 482; CHECK: llvm_mips_st_d_test: 483; CHECK: ld.d 484; CHECK: st.d [[R1:\$w[0-9]+]], 16( 485; CHECK: .size llvm_mips_st_d_test 486; 487 488define void @llvm_mips_st_d_unaligned_test() nounwind { 489entry: 490 %0 = load <2 x i64>, ptr @llvm_mips_st_d_ARG 491 tail call void @llvm.mips.st.d(<2 x i64> %0, ptr @llvm_mips_st_d_RES, i32 9) 492 ret void 493} 494 495; CHECK: llvm_mips_st_d_unaligned_test: 496; CHECK: addiu $1, $1, 9 497; CHECK: ld.d 498; CHECK: st.d [[R1:\$w[0-9]+]], 0($1) 499; CHECK: .size llvm_mips_st_d_unaligned_test 500; 501 502define void @llvm_mips_st_d_valid_range_tests() nounwind { 503entry: 504 %0 = load <2 x i64>, ptr @llvm_mips_st_d_ARG 505 tail call void @llvm.mips.st.d(<2 x i64> %0, ptr @llvm_mips_st_d_RES, i32 -4096) 506 tail call void @llvm.mips.st.d(<2 x i64> %0, ptr @llvm_mips_st_d_RES, i32 4088) 507 ret void 508} 509 510; CHECK: llvm_mips_st_d_valid_range_tests: 511; CHECK: ld.d 512; CHECK-DAG: st.d [[R1:\$w[0-9]+]], -4096( 513; CHECK-DAG: st.d [[R1:\$w[0-9]+]], 4088( 514; CHECK: .size llvm_mips_st_d_valid_range_tests 515; 516 517define void @llvm_mips_st_d_invalid_range_tests() nounwind { 518entry: 519 %0 = load <2 x i64>, ptr @llvm_mips_st_d_ARG 520 tail call void @llvm.mips.st.d(<2 x i64> %0, ptr @llvm_mips_st_d_RES, i32 -4104) 521 tail call void @llvm.mips.st.d(<2 x i64> %0, ptr @llvm_mips_st_d_RES, i32 4096) 522 ret void 523} 524 525; CHECK: llvm_mips_st_d_invalid_range_tests: 526; CHECK: addiu $2, $1, 4096 527; CHECK: ld.d 528; CHECK: st.d [[R1:\$w[0-9]+]], 0( 529; CHECK: addiu $1, $1, -4104 530; CHECK: st.d [[R1:\$w[0-9]+]], 0( 531; CHECK: .size llvm_mips_st_d_invalid_range_tests 532; 533