xref: /llvm-project/llvm/test/CodeGen/Mips/ins.ll (revision ae26f50aea4ef1a6c7058019f0db11a91bbcdade)
11ad84d79Syingopq; RUN: llc -O3 -mcpu=mips32r2 -mtriple=mipsel-linux-gnu < %s -o - \
21ad84d79Syingopq; RUN:   | FileCheck %s --check-prefixes=MIPS32R2
3*ae26f50aSFangrui Song; RUN: llc -O3 -mcpu=mips64r2 -mtriple=mips64el  < %s \
41ad84d79Syingopq; RUN:   | FileCheck %s --check-prefixes=MIPS64R2
51ad84d79Syingopq
61ad84d79Syingopqdefine i32 @or_and_shl(i32 %a, i32 %b) {
71ad84d79Syingopq; MIPS32R2-LABEL: or_and_shl:
81ad84d79Syingopq; MIPS32R2:       # %bb.0: # %entry
91ad84d79Syingopq; MIPS32R2-NEXT:    ins $4, $5, 31, 1
101ad84d79Syingopq; MIPS32R2-NEXT:    jr $ra
111ad84d79Syingopq; MIPS32R2-NEXT:    move $2, $4
121ad84d79Syingopq
131ad84d79Syingopqentry:
141ad84d79Syingopq  %shl = shl i32 %b, 31
151ad84d79Syingopq  %and = and i32 %a, 2147483647
161ad84d79Syingopq  %or = or i32 %and, %shl
171ad84d79Syingopq  ret i32 %or
181ad84d79Syingopq}
191ad84d79Syingopq
201ad84d79Syingopqdefine i32 @or_shl_and(i32 %a, i32 %b) {
211ad84d79Syingopq; MIPS32R2-LABEL: or_shl_and:
221ad84d79Syingopq; MIPS32R2:       # %bb.0: # %entry
231ad84d79Syingopq; MIPS32R2-NEXT:    ins $4, $5, 31, 1
241ad84d79Syingopq; MIPS32R2-NEXT:    jr $ra
251ad84d79Syingopq; MIPS32R2-NEXT:    move $2, $4
261ad84d79Syingopq
271ad84d79Syingopqentry:
281ad84d79Syingopq  %shl = shl i32 %b, 31
291ad84d79Syingopq  %and = and i32 %a, 2147483647
301ad84d79Syingopq  %or = or i32 %shl, %and
311ad84d79Syingopq  ret i32 %or
321ad84d79Syingopq}
331ad84d79Syingopq
341ad84d79Syingopqdefine i64 @dinsm(i64 %a, i64 %b) {
351ad84d79Syingopq; MIPS64R2-LABEL: dinsm:
361ad84d79Syingopq; MIPS64R2:       # %bb.0: # %entry
371ad84d79Syingopq; MIPS64R2-NEXT:    dinsm $4, $5, 17, 47
381ad84d79Syingopq; MIPS64R2-NEXT:    jr $ra
391ad84d79Syingopq; MIPS64R2-NEXT:    move $2, $4
401ad84d79Syingopq
411ad84d79Syingopqentry:
421ad84d79Syingopq  %shl = shl i64 %b, 17
431ad84d79Syingopq  %and = and i64 %a, 131071
441ad84d79Syingopq  %or = or i64 %shl, %and
451ad84d79Syingopq  ret i64 %or
461ad84d79Syingopq}
471ad84d79Syingopq
481ad84d79Syingopqdefine i64 @dinsu(i64 %a, i64 %b) {
491ad84d79Syingopq; MIPS64R2-LABEL: dinsu:
501ad84d79Syingopq; MIPS64R2:       # %bb.0: # %entry
511ad84d79Syingopq; MIPS64R2-NEXT:    dinsu $4, $5, 35, 29
521ad84d79Syingopq; MIPS64R2-NEXT:    jr $ra
531ad84d79Syingopq; MIPS64R2-NEXT:    move $2, $4
541ad84d79Syingopq
551ad84d79Syingopqentry:
561ad84d79Syingopq  %shl = shl i64 %b, 35
571ad84d79Syingopq  %and = and i64 %a, 34359738367
581ad84d79Syingopq  %or = or i64 %shl, %and
591ad84d79Syingopq  ret i64 %or
601ad84d79Syingopq}
61