xref: /llvm-project/llvm/test/CodeGen/Mips/ins.ll (revision ae26f50aea4ef1a6c7058019f0db11a91bbcdade)
1; RUN: llc -O3 -mcpu=mips32r2 -mtriple=mipsel-linux-gnu < %s -o - \
2; RUN:   | FileCheck %s --check-prefixes=MIPS32R2
3; RUN: llc -O3 -mcpu=mips64r2 -mtriple=mips64el  < %s \
4; RUN:   | FileCheck %s --check-prefixes=MIPS64R2
5
6define i32 @or_and_shl(i32 %a, i32 %b) {
7; MIPS32R2-LABEL: or_and_shl:
8; MIPS32R2:       # %bb.0: # %entry
9; MIPS32R2-NEXT:    ins $4, $5, 31, 1
10; MIPS32R2-NEXT:    jr $ra
11; MIPS32R2-NEXT:    move $2, $4
12
13entry:
14  %shl = shl i32 %b, 31
15  %and = and i32 %a, 2147483647
16  %or = or i32 %and, %shl
17  ret i32 %or
18}
19
20define i32 @or_shl_and(i32 %a, i32 %b) {
21; MIPS32R2-LABEL: or_shl_and:
22; MIPS32R2:       # %bb.0: # %entry
23; MIPS32R2-NEXT:    ins $4, $5, 31, 1
24; MIPS32R2-NEXT:    jr $ra
25; MIPS32R2-NEXT:    move $2, $4
26
27entry:
28  %shl = shl i32 %b, 31
29  %and = and i32 %a, 2147483647
30  %or = or i32 %shl, %and
31  ret i32 %or
32}
33
34define i64 @dinsm(i64 %a, i64 %b) {
35; MIPS64R2-LABEL: dinsm:
36; MIPS64R2:       # %bb.0: # %entry
37; MIPS64R2-NEXT:    dinsm $4, $5, 17, 47
38; MIPS64R2-NEXT:    jr $ra
39; MIPS64R2-NEXT:    move $2, $4
40
41entry:
42  %shl = shl i64 %b, 17
43  %and = and i64 %a, 131071
44  %or = or i64 %shl, %and
45  ret i64 %or
46}
47
48define i64 @dinsu(i64 %a, i64 %b) {
49; MIPS64R2-LABEL: dinsu:
50; MIPS64R2:       # %bb.0: # %entry
51; MIPS64R2-NEXT:    dinsu $4, $5, 35, 29
52; MIPS64R2-NEXT:    jr $ra
53; MIPS64R2-NEXT:    move $2, $4
54
55entry:
56  %shl = shl i64 %b, 35
57  %and = and i64 %a, 34359738367
58  %or = or i64 %shl, %and
59  ret i64 %or
60}
61