xref: /llvm-project/llvm/test/CodeGen/Mips/inlineasm-constraint-reg64.ll (revision ae26f50aea4ef1a6c7058019f0db11a91bbcdade)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2;
3; Register constraint "r" shouldn't take long long unless
4; The target is 64 bit.
5;
6;
7; RUN: llc -mtriple=mips64el -mcpu=mips64r2 -target-abi=n64 < %s | FileCheck %s
8
9
10define i32 @main() nounwind {
11; CHECK-LABEL: main:
12; CHECK:       # %bb.0: # %entry
13; CHECK-NEXT:    daddiu $1, $zero, 7
14; CHECK-NEXT:    #APP
15; CHECK-NEXT:    .set push
16; CHECK-NEXT:    .set at
17; CHECK-NEXT:    .set macro
18; CHECK-NEXT:    .set reorder
19; CHECK-EMPTY:
20; CHECK-NEXT:    addiu $1, $1, 3
21; CHECK-EMPTY:
22; CHECK-NEXT:    .set pop
23; CHECK-NEXT:    #NO_APP
24; CHECK-NEXT:    jr $ra
25; CHECK-NEXT:    addiu $2, $zero, 0
26entry:
27
28
29; r with long long
30  tail call i64 asm sideeffect "addiu $0, $1, $2", "=r,r,i"(i64 7, i64 3) nounwind
31  ret i32 0
32}
33
34