xref: /llvm-project/llvm/test/CodeGen/Mips/fcmp.ll (revision ae26f50aea4ef1a6c7058019f0db11a91bbcdade) 
1; RUN: llc < %s -mtriple=mips -mcpu=mips32 | \
2; RUN:    FileCheck %s -check-prefixes=ALL,32-C
3; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 | \
4; RUN:    FileCheck %s -check-prefixes=ALL,32-C
5; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 | \
6; RUN:    FileCheck %s -check-prefixes=ALL,32-CMP
7; RUN: llc < %s -mtriple=mips64 -mcpu=mips4 | \
8; RUN:    FileCheck %s -check-prefixes=ALL,64-C
9; RUN: llc < %s -mtriple=mips64 -mcpu=mips64 | \
10; RUN:    FileCheck %s -check-prefixes=ALL,64-C
11; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r2 | \
12; RUN:    FileCheck %s -check-prefixes=ALL,64-C
13; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r6 | \
14; RUN:    FileCheck %s -check-prefixes=ALL,64-CMP
15; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
16; RUN:    -check-prefixes=ALL,MM,MM32R3
17; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
18; RUN:    -check-prefixes=ALL,MM,MMR6,MM32R6
19
20define i32 @false_f32(float %a, float %b) nounwind {
21; ALL-LABEL: false_f32:
22; 32-C:          addiu $2, $zero, 0
23
24; 32-CMP:        addiu $2, $zero, 0
25
26; 64-C:          addiu $2, $zero, 0
27
28; 64-CMP:        addiu $2, $zero, 0
29
30; MM-DAG:        li16 $2, 0
31
32  %1 = fcmp false float %a, %b
33  %2 = zext i1 %1 to i32
34  ret i32 %2
35}
36
37define i32 @oeq_f32(float %a, float %b) nounwind {
38; ALL-LABEL: oeq_f32:
39
40; 32-C-DAG:      addiu $2, $zero, 1
41; 32-C-DAG:      c.eq.s $f12, $f14
42; 32-C:          movf $2, $zero, $fcc0
43
44; 64-C-DAG:      addiu $2, $zero, 1
45; 64-C-DAG:      c.eq.s $f12, $f13
46; 64-C:          movf $2, $zero, $fcc0
47
48; 32-CMP-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
49; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
50; 32-CMP-DAG:    andi $2, $[[T1]], 1
51
52; 64-CMP-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
53; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
54; 64-CMP-DAG:    andi $2, $[[T1]], 1
55
56; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
57; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
58; MM32R3-DAG:    c.eq.s $f12, $f14
59; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
60
61; MM32R6-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
62; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
63; MMR6-DAG:      andi16 $2, $[[T1]], 1
64
65  %1 = fcmp oeq float %a, %b
66  %2 = zext i1 %1 to i32
67  ret i32 %2
68}
69
70define i32 @ogt_f32(float %a, float %b) nounwind {
71; ALL-LABEL: ogt_f32:
72
73; 32-C-DAG:      addiu $2, $zero, 1
74; 32-C-DAG:      c.ule.s $f12, $f14
75; 32-C:          movt $2, $zero, $fcc0
76
77; 64-C-DAG:      addiu $2, $zero, 1
78; 64-C-DAG:      c.ule.s $f12, $f13
79; 64-C:          movt $2, $zero, $fcc0
80
81; 32-CMP-DAG:    cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12
82; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
83; 32-CMP-DAG:    andi $2, $[[T1]], 1
84
85; 64-CMP-DAG:    cmp.lt.s $[[T0:f[0-9]+]], $f13, $f12
86; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
87; 64-CMP-DAG:    andi $2, $[[T1]], 1
88
89; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
90; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
91; MM32R3-DAG:    c.ule.s $f12, $f14
92; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
93
94; MM32R6-DAG:    cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12
95; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
96; MMR6-DAG:      andi16 $2, $[[T1]], 1
97
98  %1 = fcmp ogt float %a, %b
99  %2 = zext i1 %1 to i32
100  ret i32 %2
101}
102
103define i32 @oge_f32(float %a, float %b) nounwind {
104; ALL-LABEL: oge_f32:
105
106; 32-C-DAG:      addiu $2, $zero, 1
107; 32-C-DAG:      c.ult.s $f12, $f14
108; 32-C:          movt $2, $zero, $fcc0
109
110; 64-C-DAG:      addiu $2, $zero, 1
111; 64-C-DAG:      c.ult.s $f12, $f13
112; 64-C:          movt $2, $zero, $fcc0
113
114; 32-CMP-DAG:    cmp.le.s $[[T0:f[0-9]+]], $f14, $f12
115; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
116; 32-CMP-DAG:    andi $2, $[[T1]], 1
117
118; 64-CMP-DAG:    cmp.le.s $[[T0:f[0-9]+]], $f13, $f12
119; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
120; 64-CMP-DAG:    andi $2, $[[T1]], 1
121
122; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
123; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
124; MM32R3-DAG:    c.ult.s $f12, $f14
125; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
126
127; MM32R6-DAG:    cmp.le.s $[[T0:f[0-9]+]], $f14, $f12
128; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
129; MMR6-DAG:      andi16 $2, $[[T1]], 1
130
131  %1 = fcmp oge float %a, %b
132  %2 = zext i1 %1 to i32
133  ret i32 %2
134}
135
136define i32 @olt_f32(float %a, float %b) nounwind {
137; ALL-LABEL: olt_f32:
138
139; 32-C-DAG:      addiu $2, $zero, 1
140; 32-C-DAG:      c.olt.s $f12, $f14
141; 32-C:          movf $2, $zero, $fcc0
142
143; 64-C-DAG:      addiu $2, $zero, 1
144; 64-C-DAG:      c.olt.s $f12, $f13
145; 64-C:          movf $2, $zero, $fcc0
146
147; 32-CMP-DAG:    cmp.lt.s $[[T0:f[0-9]+]], $f12, $f14
148; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
149; 32-CMP-DAG:    andi $2, $[[T1]], 1
150
151; 64-CMP-DAG:    cmp.lt.s $[[T0:f[0-9]+]], $f12, $f13
152; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
153; 64-CMP-DAG:    andi $2, $[[T1]], 1
154
155; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
156; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
157; MM32R3-DAG:    c.olt.s $f12, $f14
158; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
159
160; MM32R6-DAG:    cmp.lt.s $[[T0:f[0-9]+]], $f12, $f14
161; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
162; MMR6-DAG:      andi16 $2, $[[T1]], 1
163
164  %1 = fcmp olt float %a, %b
165  %2 = zext i1 %1 to i32
166  ret i32 %2
167}
168
169define i32 @ole_f32(float %a, float %b) nounwind {
170; ALL-LABEL: ole_f32:
171
172; 32-C-DAG:      addiu $2, $zero, 1
173; 32-C-DAG:      c.ole.s $f12, $f14
174; 32-C:          movf $2, $zero, $fcc0
175
176; 64-C-DAG:      addiu $2, $zero, 1
177; 64-C-DAG:      c.ole.s $f12, $f13
178; 64-C:          movf $2, $zero, $fcc0
179
180; 32-CMP-DAG:    cmp.le.s $[[T0:f[0-9]+]], $f12, $f14
181; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
182; 32-CMP-DAG:    andi $2, $[[T1]], 1
183
184; 64-CMP-DAG:    cmp.le.s $[[T0:f[0-9]+]], $f12, $f13
185; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
186; 64-CMP-DAG:    andi $2, $[[T1]], 1
187
188; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
189; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
190; MM32R3-DAG:    c.ole.s $f12, $f14
191; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
192
193; MM32R6-DAG:    cmp.le.s $[[T0:f[0-9]+]], $f12, $f14
194; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
195; MMR6-DAG:      andi16 $2, $[[T1]], 1
196
197  %1 = fcmp ole float %a, %b
198  %2 = zext i1 %1 to i32
199  ret i32 %2
200}
201
202define i32 @one_f32(float %a, float %b) nounwind {
203; ALL-LABEL: one_f32:
204
205; 32-C-DAG:      addiu $2, $zero, 1
206; 32-C-DAG:      c.ueq.s $f12, $f14
207; 32-C:          movt $2, $zero, $fcc0
208
209; 64-C-DAG:      addiu $2, $zero, 1
210; 64-C-DAG:      c.ueq.s $f12, $f13
211; 64-C:          movt $2, $zero, $fcc0
212
213; 32-CMP-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
214; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
215; 32-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
216; 32-CMP-DAG:    andi $2, $[[T2]], 1
217
218; 64-CMP-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
219; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
220; 64-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
221; 64-CMP-DAG:    andi $2, $[[T2]], 1
222
223; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
224; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
225; MM32R3-DAG:    c.ueq.s $f12, $f14
226; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
227
228; MM32R6-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
229; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
230; MMR6-DAG:      not $[[T2:[0-9]+]], $[[T1]]
231; MMR6-DAG:      andi16 $2, $[[T2]], 1
232
233  %1 = fcmp one float %a, %b
234  %2 = zext i1 %1 to i32
235  ret i32 %2
236}
237
238define i32 @ord_f32(float %a, float %b) nounwind {
239; ALL-LABEL: ord_f32:
240
241; 32-C-DAG:      addiu $2, $zero, 1
242; 32-C-DAG:      c.un.s $f12, $f14
243; 32-C:          movt $2, $zero, $fcc0
244
245; 64-C-DAG:      addiu $2, $zero, 1
246; 64-C-DAG:      c.un.s $f12, $f13
247; 64-C:          movt $2, $zero, $fcc0
248
249; 32-CMP-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
250; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
251; 32-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
252; 32-CMP-DAG:    andi $2, $[[T2]], 1
253
254; 64-CMP-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
255; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
256; 64-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
257; 64-CMP-DAG:    andi $2, $[[T2]], 1
258
259; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
260; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
261; MM32R3-DAG:    c.un.s  $f12, $f14
262; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
263
264; MM32R6-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
265; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
266; MMR6-DAG:      not $[[T2:[0-9]+]], $[[T1]]
267; MMR6-DAG:      andi16 $2, $[[T2]], 1
268
269  %1 = fcmp ord float %a, %b
270  %2 = zext i1 %1 to i32
271  ret i32 %2
272}
273
274define i32 @ueq_f32(float %a, float %b) nounwind {
275; ALL-LABEL: ueq_f32:
276
277; 32-C-DAG:      addiu $2, $zero, 1
278; 32-C-DAG:      c.ueq.s $f12, $f14
279; 32-C:          movf $2, $zero, $fcc0
280
281; 64-C-DAG:      addiu $2, $zero, 1
282; 64-C-DAG:      c.ueq.s $f12, $f13
283; 64-C:          movf $2, $zero, $fcc0
284
285; 32-CMP-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
286; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
287; 32-CMP-DAG:    andi $2, $[[T1]], 1
288
289; 64-CMP-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
290; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
291; 64-CMP-DAG:    andi $2, $[[T1]], 1
292
293; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
294; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
295; MM32R3-DAG:    c.ueq.s $f12, $f14
296; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
297
298; MM32R6-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
299; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
300; MMR6-DAG:      andi16 $2, $[[T1]], 1
301
302  %1 = fcmp ueq float %a, %b
303  %2 = zext i1 %1 to i32
304  ret i32 %2
305}
306
307define i32 @ugt_f32(float %a, float %b) nounwind {
308; ALL-LABEL: ugt_f32:
309
310; 32-C-DAG:      addiu $2, $zero, 1
311; 32-C-DAG:      c.ole.s $f12, $f14
312; 32-C:          movt $2, $zero, $fcc0
313
314; 64-C-DAG:      addiu $2, $zero, 1
315; 64-C-DAG:      c.ole.s $f12, $f13
316; 64-C:          movt $2, $zero, $fcc0
317
318; 32-CMP-DAG:    cmp.ult.s $[[T0:f[0-9]+]], $f14, $f12
319; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
320; 32-CMP-DAG:    andi $2, $[[T1]], 1
321
322; 64-CMP-DAG:    cmp.ult.s $[[T0:f[0-9]+]], $f13, $f12
323; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
324; 64-CMP-DAG:    andi $2, $[[T1]], 1
325
326; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
327; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
328; MM32R3-DAG:    c.ole.s $f12, $f14
329; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
330
331; MM32R6-DAG:    cmp.ult.s $[[T0:f[0-9]+]], $f14, $f12
332; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
333; MMR6-DAG:      andi16 $2, $[[T1]], 1
334
335  %1 = fcmp ugt float %a, %b
336  %2 = zext i1 %1 to i32
337  ret i32 %2
338}
339
340define i32 @uge_f32(float %a, float %b) nounwind {
341; ALL-LABEL: uge_f32:
342
343; 32-C-DAG:      addiu $2, $zero, 1
344; 32-C-DAG:      c.olt.s $f12, $f14
345; 32-C:          movt $2, $zero, $fcc0
346
347; 64-C-DAG:      addiu $2, $zero, 1
348; 64-C-DAG:      c.olt.s $f12, $f13
349; 64-C:          movt $2, $zero, $fcc0
350
351; 32-CMP-DAG:    cmp.ule.s $[[T0:f[0-9]+]], $f14, $f12
352; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
353; 32-CMP-DAG:    andi $2, $[[T1]], 1
354
355; 64-CMP-DAG:    cmp.ule.s $[[T0:f[0-9]+]], $f13, $f12
356; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
357; 64-CMP-DAG:    andi $2, $[[T1]], 1
358
359; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
360; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
361; MM32R3-DAG:    c.olt.s $f12, $f14
362; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
363
364; MM32R6-DAG:    cmp.ule.s $[[T0:f[0-9]+]], $f14, $f12
365; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
366; MMR6-DAG:      andi16 $2, $[[T1]], 1
367
368  %1 = fcmp uge float %a, %b
369  %2 = zext i1 %1 to i32
370  ret i32 %2
371}
372
373define i32 @ult_f32(float %a, float %b) nounwind {
374; ALL-LABEL: ult_f32:
375
376; 32-C-DAG:      addiu $2, $zero, 1
377; 32-C-DAG:      c.ult.s $f12, $f14
378; 32-C:          movf $2, $zero, $fcc0
379
380; 64-C-DAG:      addiu $2, $zero, 1
381; 64-C-DAG:      c.ult.s $f12, $f13
382; 64-C:          movf $2, $zero, $fcc0
383
384; 32-CMP-DAG:    cmp.ult.s $[[T0:f[0-9]+]], $f12, $f14
385; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
386; 32-CMP-DAG:    andi $2, $[[T1]], 1
387
388; 64-CMP-DAG:    cmp.ult.s $[[T0:f[0-9]+]], $f12, $f13
389; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
390; 64-CMP-DAG:    andi $2, $[[T1]], 1
391
392; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
393; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
394; MM32R3-DAG:    c.ult.s $f12, $f14
395; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
396
397; MM32R6-DAG:    cmp.ult.s $[[T0:f[0-9]+]], $f12, $f14
398; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
399; MMR6-DAG:      andi16 $2, $[[T1]], 1
400
401  %1 = fcmp ult float %a, %b
402  %2 = zext i1 %1 to i32
403  ret i32 %2
404}
405
406define i32 @ule_f32(float %a, float %b) nounwind {
407; ALL-LABEL: ule_f32:
408
409; 32-C-DAG:      addiu $2, $zero, 1
410; 32-C-DAG:      c.ule.s $f12, $f14
411; 32-C:          movf $2, $zero, $fcc0
412
413; 64-C-DAG:      addiu $2, $zero, 1
414; 64-C-DAG:      c.ule.s $f12, $f13
415; 64-C:          movf $2, $zero, $fcc0
416
417; 32-CMP-DAG:    cmp.ule.s $[[T0:f[0-9]+]], $f12, $f14
418; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
419; 32-CMP-DAG:    andi $2, $[[T1]], 1
420
421; 64-CMP-DAG:    cmp.ule.s $[[T0:f[0-9]+]], $f12, $f13
422; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
423; 64-CMP-DAG:    andi $2, $[[T1]], 1
424
425; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
426; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
427; MM32R3-DAG:    c.ule.s $f12, $f14
428; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
429
430; MM32R6-DAG:    cmp.ule.s $[[T0:f[0-9]+]], $f12, $f14
431; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
432; MMR6-DAG:      andi16 $2, $[[T1]], 1
433
434  %1 = fcmp ule float %a, %b
435  %2 = zext i1 %1 to i32
436  ret i32 %2
437}
438
439define i32 @une_f32(float %a, float %b) nounwind {
440; ALL-LABEL: une_f32:
441
442; 32-C-DAG:      addiu $2, $zero, 1
443; 32-C-DAG:      c.eq.s $f12, $f14
444; 32-C:          movt $2, $zero, $fcc0
445
446; 64-C-DAG:      addiu $2, $zero, 1
447; 64-C-DAG:      c.eq.s $f12, $f13
448; 64-C:          movt $2, $zero, $fcc0
449
450; 32-CMP-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
451; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
452; 32-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
453; 32-CMP-DAG:    andi $2, $[[T2]], 1
454
455; 64-CMP-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
456; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
457; 64-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
458; 64-CMP-DAG:    andi $2, $[[T2]], 1
459
460; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
461; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
462; MM32R3-DAG:    c.eq.s $f12, $f14
463; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
464
465; MM32R6-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
466; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
467; MMR6-DAG:      not $[[T2:[0-9]+]], $[[T1]]
468; MMR6-DAG:      andi16 $2, $[[T2]], 1
469
470  %1 = fcmp une float %a, %b
471  %2 = zext i1 %1 to i32
472  ret i32 %2
473}
474
475define i32 @uno_f32(float %a, float %b) nounwind {
476; ALL-LABEL: uno_f32:
477
478; 32-C-DAG:      addiu $2, $zero, 1
479; 32-C-DAG:      c.un.s $f12, $f14
480; 32-C:          movf $2, $zero, $fcc0
481
482; 64-C-DAG:      addiu $2, $zero, 1
483; 64-C-DAG:      c.un.s $f12, $f13
484; 64-C:          movf $2, $zero, $fcc0
485
486; 32-CMP-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
487; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
488; 32-CMP-DAG:    andi $2, $[[T1]], 1
489
490; 64-CMP-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
491; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
492; 64-CMP-DAG:    andi $2, $[[T1]], 1
493
494; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
495; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
496; MM32R3-DAG:    c.un.s $f12, $f14
497; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
498
499; MM32R6-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
500; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
501; MMR6-DAG:      andi16 $2, $[[T1]], 1
502
503  %1 = fcmp uno float %a, %b
504  %2 = zext i1 %1 to i32
505  ret i32 %2
506}
507
508define i32 @true_f32(float %a, float %b) nounwind {
509; ALL-LABEL: true_f32:
510; 32-C:          addiu $2, $zero, 1
511
512; 32-CMP:        addiu $2, $zero, 1
513
514; 64-C:          addiu $2, $zero, 1
515
516; 64-CMP:        addiu $2, $zero, 1
517
518; MM-DAG:        li16 $2, 1
519
520  %1 = fcmp true float %a, %b
521  %2 = zext i1 %1 to i32
522  ret i32 %2
523}
524
525define i32 @false_f64(double %a, double %b) nounwind {
526; ALL-LABEL: false_f64:
527; 32-C:          addiu $2, $zero, 0
528
529; 32-CMP:        addiu $2, $zero, 0
530
531; 64-C:          addiu $2, $zero, 0
532
533; 64-CMP:        addiu $2, $zero, 0
534
535; MM-DAG:        li16 $2, 0
536
537  %1 = fcmp false double %a, %b
538  %2 = zext i1 %1 to i32
539  ret i32 %2
540}
541
542define i32 @oeq_f64(double %a, double %b) nounwind {
543; ALL-LABEL: oeq_f64:
544
545; 32-C-DAG:      addiu $2, $zero, 1
546; 32-C-DAG:      c.eq.d $f12, $f14
547; 32-C:          movf $2, $zero, $fcc0
548
549; 64-C-DAG:      addiu $2, $zero, 1
550; 64-C-DAG:      c.eq.d $f12, $f13
551; 64-C:          movf $2, $zero, $fcc0
552
553; 32-CMP-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
554; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
555; 32-CMP-DAG:    andi $2, $[[T1]], 1
556
557; 64-CMP-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
558; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
559; 64-CMP-DAG:    andi $2, $[[T1]], 1
560
561; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
562; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
563; MM32R3-DAG:    c.eq.d $f12, $f14
564; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
565
566; MM32R6-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
567; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
568; MMR6-DAG:      andi16 $2, $[[T1]], 1
569
570  %1 = fcmp oeq double %a, %b
571  %2 = zext i1 %1 to i32
572  ret i32 %2
573}
574
575define i32 @ogt_f64(double %a, double %b) nounwind {
576; ALL-LABEL: ogt_f64:
577
578; 32-C-DAG:      addiu $2, $zero, 1
579; 32-C-DAG:      c.ule.d $f12, $f14
580; 32-C:          movt $2, $zero, $fcc0
581
582; 64-C-DAG:      addiu $2, $zero, 1
583; 64-C-DAG:      c.ule.d $f12, $f13
584; 64-C:          movt $2, $zero, $fcc0
585
586; 32-CMP-DAG:    cmp.lt.d $[[T0:f[0-9]+]], $f14, $f12
587; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
588; 32-CMP-DAG:    andi $2, $[[T1]], 1
589
590; 64-CMP-DAG:    cmp.lt.d $[[T0:f[0-9]+]], $f13, $f12
591; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
592; 64-CMP-DAG:    andi $2, $[[T1]], 1
593
594; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
595; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
596; MM32R3-DAG:    c.ule.d $f12, $f14
597; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
598
599; MM32R6-DAG:    cmp.lt.d $[[T0:f[0-9]+]], $f14, $f12
600; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
601; MMR6-DAG:      andi16 $2, $[[T1]], 1
602
603  %1 = fcmp ogt double %a, %b
604  %2 = zext i1 %1 to i32
605  ret i32 %2
606}
607
608define i32 @oge_f64(double %a, double %b) nounwind {
609; ALL-LABEL: oge_f64:
610
611; 32-C-DAG:      addiu $2, $zero, 1
612; 32-C-DAG:      c.ult.d $f12, $f14
613; 32-C:          movt $2, $zero, $fcc0
614
615; 64-C-DAG:      addiu $2, $zero, 1
616; 64-C-DAG:      c.ult.d $f12, $f13
617; 64-C:          movt $2, $zero, $fcc0
618
619; 32-CMP-DAG:    cmp.le.d $[[T0:f[0-9]+]], $f14, $f12
620; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
621; 32-CMP-DAG:    andi $2, $[[T1]], 1
622
623; 64-CMP-DAG:    cmp.le.d $[[T0:f[0-9]+]], $f13, $f12
624; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
625; 64-CMP-DAG:    andi $2, $[[T1]], 1
626
627; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
628; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
629; MM32R3-DAG:    c.ult.d $f12, $f14
630; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
631
632; MM32R6-DAG:    cmp.le.d $[[T0:f[0-9]+]], $f14, $f12
633; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
634; MMR6-DAG:      andi16 $2, $[[T1]], 1
635
636  %1 = fcmp oge double %a, %b
637  %2 = zext i1 %1 to i32
638  ret i32 %2
639}
640
641define i32 @olt_f64(double %a, double %b) nounwind {
642; ALL-LABEL: olt_f64:
643
644; 32-C-DAG:      addiu $2, $zero, 1
645; 32-C-DAG:      c.olt.d $f12, $f14
646; 32-C:          movf $2, $zero, $fcc0
647
648; 64-C-DAG:      addiu $2, $zero, 1
649; 64-C-DAG:      c.olt.d $f12, $f13
650; 64-C:          movf $2, $zero, $fcc0
651
652; 32-CMP-DAG:    cmp.lt.d $[[T0:f[0-9]+]], $f12, $f14
653; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
654; 32-CMP-DAG:    andi $2, $[[T1]], 1
655
656; 64-CMP-DAG:    cmp.lt.d $[[T0:f[0-9]+]], $f12, $f13
657; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
658; 64-CMP-DAG:    andi $2, $[[T1]], 1
659
660; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
661; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
662; MM32R3-DAG:    c.olt.d $f12, $f14
663; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
664
665; MM32R6-DAG:    cmp.lt.d $[[T0:f[0-9]+]], $f12, $f14
666; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
667; MMR6-DAG:      andi16 $2, $[[T1]], 1
668
669  %1 = fcmp olt double %a, %b
670  %2 = zext i1 %1 to i32
671  ret i32 %2
672}
673
674define i32 @ole_f64(double %a, double %b) nounwind {
675; ALL-LABEL: ole_f64:
676
677; 32-C-DAG:      addiu $2, $zero, 1
678; 32-C-DAG:      c.ole.d $f12, $f14
679; 32-C:          movf $2, $zero, $fcc0
680
681; 64-C-DAG:      addiu $2, $zero, 1
682; 64-C-DAG:      c.ole.d $f12, $f13
683; 64-C:          movf $2, $zero, $fcc0
684
685; 32-CMP-DAG:    cmp.le.d $[[T0:f[0-9]+]], $f12, $f14
686; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
687; 32-CMP-DAG:    andi $2, $[[T1]], 1
688
689; 64-CMP-DAG:    cmp.le.d $[[T0:f[0-9]+]], $f12, $f13
690; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
691; 64-CMP-DAG:    andi $2, $[[T1]], 1
692
693; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
694; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
695; MM32R3-DAG:    c.ole.d $f12, $f14
696; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
697
698; MM32R6-DAG:    cmp.le.d $[[T0:f[0-9]+]], $f12, $f14
699; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
700; MMR6-DAG:      andi16 $2, $[[T1]], 1
701
702  %1 = fcmp ole double %a, %b
703  %2 = zext i1 %1 to i32
704  ret i32 %2
705}
706
707define i32 @one_f64(double %a, double %b) nounwind {
708; ALL-LABEL: one_f64:
709
710; 32-C-DAG:      addiu $2, $zero, 1
711; 32-C-DAG:      c.ueq.d $f12, $f14
712; 32-C:          movt $2, $zero, $fcc0
713
714; 64-C-DAG:      addiu $2, $zero, 1
715; 64-C-DAG:      c.ueq.d $f12, $f13
716; 64-C:          movt $2, $zero, $fcc0
717
718; 32-CMP-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
719; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
720; 32-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
721; 32-CMP-DAG:    andi $2, $[[T2]], 1
722
723; 64-CMP-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
724; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
725; 64-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
726; 64-CMP-DAG:    andi $2, $[[T2]], 1
727
728; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
729; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
730; MM32R3-DAG:    c.ueq.d $f12, $f14
731; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
732
733; MM32R6-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
734; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
735; MMR6-DAG:      not $[[T2:[0-9]+]], $[[T1]]
736; MMR6-DAG:      andi16 $2, $[[T2]], 1
737
738  %1 = fcmp one double %a, %b
739  %2 = zext i1 %1 to i32
740  ret i32 %2
741}
742
743define i32 @ord_f64(double %a, double %b) nounwind {
744; ALL-LABEL: ord_f64:
745
746; 32-C-DAG:      addiu $2, $zero, 1
747; 32-C-DAG:      c.un.d $f12, $f14
748; 32-C:          movt $2, $zero, $fcc0
749
750; 64-C-DAG:      addiu $2, $zero, 1
751; 64-C-DAG:      c.un.d $f12, $f13
752; 64-C:          movt $2, $zero, $fcc0
753
754; 32-CMP-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
755; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
756; 32-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
757; 32-CMP-DAG:    andi $2, $[[T2]], 1
758
759; 64-CMP-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
760; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
761; 64-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
762; 64-CMP-DAG:    andi $2, $[[T2]], 1
763
764; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
765; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
766; MM32R3-DAG:    c.un.d $f12, $f14
767; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
768
769; MM32R6-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
770; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
771; MMR6-DAG:      not $[[T2:[0-9]+]], $[[T1]]
772; MMR6-DAG:      andi16 $2, $[[T2]], 1
773
774  %1 = fcmp ord double %a, %b
775  %2 = zext i1 %1 to i32
776  ret i32 %2
777}
778
779define i32 @ueq_f64(double %a, double %b) nounwind {
780; ALL-LABEL: ueq_f64:
781
782; 32-C-DAG:      addiu $2, $zero, 1
783; 32-C-DAG:      c.ueq.d $f12, $f14
784; 32-C:          movf $2, $zero, $fcc0
785
786; 64-C-DAG:      addiu $2, $zero, 1
787; 64-C-DAG:      c.ueq.d $f12, $f13
788; 64-C:          movf $2, $zero, $fcc0
789
790; 32-CMP-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
791; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
792; 32-CMP-DAG:    andi $2, $[[T1]], 1
793
794; 64-CMP-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
795; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
796; 64-CMP-DAG:    andi $2, $[[T1]], 1
797
798; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
799; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
800; MM32R3-DAG:    c.ueq.d $f12, $f14
801; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
802
803; MM32R6-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
804; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
805; MMR6-DAG:      andi16 $2, $[[T1]], 1
806
807  %1 = fcmp ueq double %a, %b
808  %2 = zext i1 %1 to i32
809  ret i32 %2
810}
811
812define i32 @ugt_f64(double %a, double %b) nounwind {
813; ALL-LABEL: ugt_f64:
814
815; 32-C-DAG:      addiu $2, $zero, 1
816; 32-C-DAG:      c.ole.d $f12, $f14
817; 32-C:          movt $2, $zero, $fcc0
818
819; 64-C-DAG:      addiu $2, $zero, 1
820; 64-C-DAG:      c.ole.d $f12, $f13
821; 64-C:          movt $2, $zero, $fcc0
822
823; 32-CMP-DAG:    cmp.ult.d $[[T0:f[0-9]+]], $f14, $f12
824; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
825; 32-CMP-DAG:    andi $2, $[[T1]], 1
826
827; 64-CMP-DAG:    cmp.ult.d $[[T0:f[0-9]+]], $f13, $f12
828; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
829; 64-CMP-DAG:    andi $2, $[[T1]], 1
830
831; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
832; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
833; MM32R3-DAG:    c.ole.d $f12, $f14
834; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
835
836; MM32R6-DAG:    cmp.ult.d $[[T0:f[0-9]+]], $f14, $f12
837; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
838; MMR6-DAG:      andi16 $2, $[[T1]], 1
839
840  %1 = fcmp ugt double %a, %b
841  %2 = zext i1 %1 to i32
842  ret i32 %2
843}
844
845define i32 @uge_f64(double %a, double %b) nounwind {
846; ALL-LABEL: uge_f64:
847
848; 32-C-DAG:      addiu $2, $zero, 1
849; 32-C-DAG:      c.olt.d $f12, $f14
850; 32-C:          movt $2, $zero, $fcc0
851
852; 64-C-DAG:      addiu $2, $zero, 1
853; 64-C-DAG:      c.olt.d $f12, $f13
854; 64-C:          movt $2, $zero, $fcc0
855
856; 32-CMP-DAG:    cmp.ule.d $[[T0:f[0-9]+]], $f14, $f12
857; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
858; 32-CMP-DAG:    andi $2, $[[T1]], 1
859
860; 64-CMP-DAG:    cmp.ule.d $[[T0:f[0-9]+]], $f13, $f12
861; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
862; 64-CMP-DAG:    andi $2, $[[T1]], 1
863
864; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
865; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
866; MM32R3-DAG:    c.olt.d $f12, $f14
867; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
868
869; MM32R6-DAG:    cmp.ule.d $[[T0:f[0-9]+]], $f14, $f12
870; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
871; MMR6-DAG:      andi16 $2, $[[T1]], 1
872
873  %1 = fcmp uge double %a, %b
874  %2 = zext i1 %1 to i32
875  ret i32 %2
876}
877
878define i32 @ult_f64(double %a, double %b) nounwind {
879; ALL-LABEL: ult_f64:
880
881; 32-C-DAG:      addiu $2, $zero, 1
882; 32-C-DAG:      c.ult.d $f12, $f14
883; 32-C:          movf $2, $zero, $fcc0
884
885; 64-C-DAG:      addiu $2, $zero, 1
886; 64-C-DAG:      c.ult.d $f12, $f13
887; 64-C:          movf $2, $zero, $fcc0
888
889; 32-CMP-DAG:    cmp.ult.d $[[T0:f[0-9]+]], $f12, $f14
890; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
891; 32-CMP-DAG:    andi $2, $[[T1]], 1
892
893; 64-CMP-DAG:    cmp.ult.d $[[T0:f[0-9]+]], $f12, $f13
894; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
895; 64-CMP-DAG:    andi $2, $[[T1]], 1
896
897; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
898; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
899; MM32R3-DAG:    c.ult.d $f12, $f14
900; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
901
902; MM32R6-DAG:    cmp.ult.d $[[T0:f[0-9]+]], $f12, $f14
903; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
904; MMR6-DAG:      andi16 $2, $[[T1]], 1
905
906  %1 = fcmp ult double %a, %b
907  %2 = zext i1 %1 to i32
908  ret i32 %2
909}
910
911define i32 @ule_f64(double %a, double %b) nounwind {
912; ALL-LABEL: ule_f64:
913
914; 32-C-DAG:      addiu $2, $zero, 1
915; 32-C-DAG:      c.ule.d $f12, $f14
916; 32-C:          movf $2, $zero, $fcc0
917
918; 64-C-DAG:      addiu $2, $zero, 1
919; 64-C-DAG:      c.ule.d $f12, $f13
920; 64-C:          movf $2, $zero, $fcc0
921
922; 32-CMP-DAG:    cmp.ule.d $[[T0:f[0-9]+]], $f12, $f14
923; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
924; 32-CMP-DAG:    andi $2, $[[T1]], 1
925
926; 64-CMP-DAG:    cmp.ule.d $[[T0:f[0-9]+]], $f12, $f13
927; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
928; 64-CMP-DAG:    andi $2, $[[T1]], 1
929
930; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
931; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
932; MM32R3-DAG:    c.ule.d $f12, $f14
933; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
934
935; MM32R6-DAG:    cmp.ule.d $[[T0:f[0-9]+]], $f12, $f14
936; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
937; MMR6-DAG:      andi16 $2, $[[T1]], 1
938
939  %1 = fcmp ule double %a, %b
940  %2 = zext i1 %1 to i32
941  ret i32 %2
942}
943
944define i32 @une_f64(double %a, double %b) nounwind {
945; ALL-LABEL: une_f64:
946
947; 32-C-DAG:      addiu $2, $zero, 1
948; 32-C-DAG:      c.eq.d $f12, $f14
949; 32-C:          movt $2, $zero, $fcc0
950
951; 64-C-DAG:      addiu $2, $zero, 1
952; 64-C-DAG:      c.eq.d $f12, $f13
953; 64-C:          movt $2, $zero, $fcc0
954
955; 32-CMP-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
956; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
957; 32-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
958; 32-CMP-DAG:    andi $2, $[[T2]], 1
959
960; 64-CMP-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
961; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
962; 64-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
963; 64-CMP-DAG:    andi $2, $[[T2]], 1
964
965; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
966; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
967; MM32R3-DAG:    c.eq.d  $f12, $f14
968; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
969
970; MM32R6-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
971; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
972; MMR6-DAG:      not $[[T2:[0-9]+]], $[[T1]]
973; MMR6-DAG:      andi16 $2, $[[T2]], 1
974
975  %1 = fcmp une double %a, %b
976  %2 = zext i1 %1 to i32
977  ret i32 %2
978}
979
980define i32 @uno_f64(double %a, double %b) nounwind {
981; ALL-LABEL: uno_f64:
982
983; 32-C-DAG:      addiu $2, $zero, 1
984; 32-C-DAG:      c.un.d $f12, $f14
985; 32-C:          movf $2, $zero, $fcc0
986
987; 64-C-DAG:      addiu $2, $zero, 1
988; 64-C-DAG:      c.un.d $f12, $f13
989; 64-C:          movf $2, $zero, $fcc0
990
991; 32-CMP-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
992; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
993; 32-CMP-DAG:    andi $2, $[[T1]], 1
994
995; 64-CMP-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
996; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
997; 64-CMP-DAG:    andi $2, $[[T1]], 1
998
999; MM32R3-DAG:    li16 $[[T0:[0-9]+]], 0
1000; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
1001; MM32R3-DAG:    c.un.d $f12, $f14
1002; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
1003
1004; MM32R6-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
1005; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
1006; MMR6-DAG:      andi16 $2, $[[T1]], 1
1007
1008  %1 = fcmp uno double %a, %b
1009  %2 = zext i1 %1 to i32
1010  ret i32 %2
1011}
1012
1013define i32 @true_f64(double %a, double %b) nounwind {
1014; ALL-LABEL: true_f64:
1015; 32-C:          addiu $2, $zero, 1
1016
1017; 32-CMP:        addiu $2, $zero, 1
1018
1019; 64-C:          addiu $2, $zero, 1
1020
1021; 64-CMP:        addiu $2, $zero, 1
1022
1023; MM-DAG:        li16 $2, 1
1024
1025  %1 = fcmp true double %a, %b
1026  %2 = zext i1 %1 to i32
1027  ret i32 %2
1028}
1029
1030; The optimizers sometimes produce setlt instead of setolt/setult.
1031define float @bug1_f32(float %angle, float %at) #0 {
1032entry:
1033; ALL-LABEL: bug1_f32:
1034
1035; 32-C-DAG:      add.s    $[[T0:f[0-9]+]], $f14, $f12
1036; 32-C-DAG:      lwc1     $[[T1:f[0-9]+]], %lo($CPI32_0)(
1037; 32-C-DAG:      c.ole.s  $[[T0]], $[[T1]]
1038; 32-C-DAG:      bc1t
1039
1040; 32-CMP-DAG:    add.s    $[[T0:f[0-9]+]], $f14, $f12
1041; 32-CMP-DAG:    lwc1     $[[T1:f[0-9]+]], %lo($CPI32_0)(
1042; 32-CMP-DAG:    cmp.le.s $[[T2:f[0-9]+]], $[[T0]], $[[T1]]
1043; 32-CMP-DAG:    mfc1     $[[T3:[0-9]+]], $[[T2]]
1044; FIXME: This instruction is redundant.
1045; 32-CMP-DAG:    andi     $[[T4:[0-9]+]], $[[T3]], 1
1046; 32-CMP-DAG:    bnezc    $[[T4]],
1047
1048; 64-C-DAG:      add.s    $[[T0:f[0-9]+]], $f13, $f12
1049; 64-C-DAG:      lwc1     $[[T1:f[0-9]+]], %lo(.LCPI32_0)(
1050; 64-C-DAG:      c.ole.s  $[[T0]], $[[T1]]
1051; 64-C-DAG:      bc1t
1052
1053; 64-CMP-DAG:    add.s    $[[T0:f[0-9]+]], $f13, $f12
1054; 64-CMP-DAG:    lwc1     $[[T1:f[0-9]+]], %lo(.LCPI32_0)(
1055; 64-CMP-DAG:    cmp.le.s $[[T2:f[0-9]+]], $[[T0]], $[[T1]]
1056; 64-CMP-DAG:    mfc1     $[[T3:[0-9]+]], $[[T2]]
1057; FIXME: This instruction is redundant.
1058; 64-CMP-DAG:    andi     $[[T4:[0-9]+]], $[[T3]], 1
1059; 64-CMP-DAG:    bnezc    $[[T4]],
1060
1061; MM32R3-DAG:    add.s    $[[T0:f[0-9]+]], $f14, $f12
1062; MM32R3-DAG:    lui      $[[T1:[0-9]+]], %hi($CPI32_0)
1063; MM32R3-DAG:    lwc1     $[[T2:f[0-9]+]], %lo($CPI32_0)($[[T1]])
1064; MM32R3-DAG:    c.ole.s  $[[T0]], $[[T2]]
1065; MM32R3-DAG:    bc1t
1066
1067; MM32R6-DAG:    add.s    $[[T0:f[0-9]+]], $f14, $f12
1068; MM32R6-DAG:    lui      $[[T1:[0-9]+]], %hi($CPI32_0)
1069; MM32R6-DAG:    lwc1     $[[T2:f[0-9]+]], %lo($CPI32_0)($[[T1]])
1070; MM32R6-DAG:    cmp.le.s $[[T3:f[0-9]+]], $[[T0]], $[[T2]]
1071; MM32R6-DAG:    mfc1     $[[T4:[0-9]+]], $[[T3:f[0-9]+]]
1072; MM32R6-DAG:    andi16   $[[T5:[0-9]+]], $[[T4]], 1
1073; MM32R6-DAG:    bnezc    $[[T5]],
1074
1075  %add = fadd fast float %at, %angle
1076  %cmp = fcmp ogt float %add, 1.000000e+00
1077  br i1 %cmp, label %if.then, label %if.end
1078
1079if.then:
1080  %sub = fadd fast float %add, -1.000000e+00
1081  br label %if.end
1082
1083if.end:
1084  %theta.0 = phi float [ %sub, %if.then ], [ %add, %entry ]
1085  ret float %theta.0
1086}
1087
1088; The optimizers sometimes produce setlt instead of setolt/setult.
1089define double @bug1_f64(double %angle, double %at) #0 {
1090entry:
1091; ALL-LABEL: bug1_f64:
1092
1093; 32-C-DAG:      add.d    $[[T0:f[0-9]+]], $f14, $f12
1094; 32-C-DAG:      ldc1     $[[T1:f[0-9]+]], %lo($CPI33_0)(
1095; 32-C-DAG:      c.ole.d  $[[T0]], $[[T1]]
1096; 32-C-DAG:      bc1t
1097
1098; 32-CMP-DAG:    add.d    $[[T0:f[0-9]+]], $f14, $f12
1099; 32-CMP-DAG:    ldc1     $[[T1:f[0-9]+]], %lo($CPI33_0)(
1100; 32-CMP-DAG:    cmp.le.d $[[T2:f[0-9]+]], $[[T0]], $[[T1]]
1101; 32-CMP-DAG:    mfc1     $[[T3:[0-9]+]], $[[T2]]
1102; FIXME: This instruction is redundant.
1103; 32-CMP-DAG:    andi     $[[T4:[0-9]+]], $[[T3]], 1
1104; 32-CMP-DAG:    bnezc    $[[T4]],
1105
1106; 64-C-DAG:      add.d    $[[T0:f[0-9]+]], $f13, $f12
1107; 64-C-DAG:      ldc1     $[[T1:f[0-9]+]], %lo(.LCPI33_0)(
1108; 64-C-DAG:      c.ole.d  $[[T0]], $[[T1]]
1109; 64-C-DAG:      bc1t
1110
1111; 64-CMP-DAG:    add.d    $[[T0:f[0-9]+]], $f13, $f12
1112; 64-CMP-DAG:    ldc1     $[[T1:f[0-9]+]], %lo(.LCPI33_0)(
1113; 64-CMP-DAG:    cmp.le.d $[[T2:f[0-9]+]], $[[T0]], $[[T1]]
1114; 64-CMP-DAG:    mfc1     $[[T3:[0-9]+]], $[[T2]]
1115; FIXME: This instruction is redundant.
1116; 64-CMP-DAG:    andi     $[[T4:[0-9]+]], $[[T3]], 1
1117; 64-CMP-DAG:    bnezc    $[[T4]],
1118
1119; MM32R3-DAG:    add.d    $[[T0:f[0-9]+]], $f14, $f12
1120; MM32R3-DAG:    lui      $[[T1:[0-9]+]], %hi($CPI33_0)
1121; MM32R3-DAG:    ldc1     $[[T2:f[0-9]+]], %lo($CPI33_0)($[[T1]])
1122; MM32R3-DAG:    c.ole.d  $[[T0]], $[[T2]]
1123; MM32R3-DAG:    bc1t
1124
1125; MM32R6-DAG:    add.d    $[[T0:f[0-9]+]], $f14, $f12
1126; MM32R6-DAG:    lui      $[[T1:[0-9]+]], %hi($CPI33_0)
1127; MM32R6-DAG:    ldc1     $[[T2:f[0-9]+]], %lo($CPI33_0)($[[T1]])
1128; MM32R6-DAG:    cmp.le.d $[[T3:f[0-9]+]], $[[T0]], $[[T2]]
1129; MM32R6-DAG:    mfc1     $[[T4:[0-9]+]], $[[T3]]
1130; MM32R6-DAG:    andi16   $[[T5:[0-9]+]], $[[T4]], 1
1131; MM32R6-DAG:    bnezc    $[[T5]],
1132
1133  %add = fadd fast double %at, %angle
1134  %cmp = fcmp ogt double %add, 1.000000e+00
1135  br i1 %cmp, label %if.then, label %if.end
1136
1137if.then:
1138  %sub = fadd fast double %add, -1.000000e+00
1139  br label %if.end
1140
1141if.end:
1142  %theta.0 = phi double [ %sub, %if.then ], [ %add, %entry ]
1143  ret double %theta.0
1144}
1145
1146attributes #0 = { nounwind readnone "no-nans-fp-math"="true" }
1147