xref: /llvm-project/llvm/test/CodeGen/Mips/atomicops.ll (revision ae26f50aea4ef1a6c7058019f0db11a91bbcdade)
1; RUN: llc  -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
2
3@.str = private unnamed_addr constant [8 x i8] c"%d, %d\0A\00", align 1
4
5define i32 @foo(ptr %mem, i32 %val, i32 %c) nounwind {
6entry:
7  %0 = atomicrmw add ptr %mem, i32 %val seq_cst
8  %add = add nsw i32 %0, %c
9  ret i32 %add
10; 16-LABEL: foo:
11; 16:	lw	${{[0-9]+}}, %call16(__sync_synchronize)(${{[0-9]+}})
12; 16: 	lw	${{[0-9]+}}, %call16(__sync_fetch_and_add_4)(${{[0-9]+}})
13}
14
15define i32 @atomic_load_sub(ptr %mem, i32 %val, i32 %c) nounwind {
16; 16-LABEL: atomic_load_sub:
17; 16:	lw	${{[0-9]+}}, %call16(__sync_synchronize)(${{[0-9]+}})
18; 16: 	lw	${{[0-9]+}}, %call16(__sync_fetch_and_sub_4)(${{[0-9]+}})
19entry:
20  %0 = atomicrmw sub ptr %mem, i32 %val seq_cst
21  ret i32 %0
22}
23
24define i32 @main() nounwind {
25entry:
26  %x = alloca i32, align 4
27  store volatile i32 0, ptr %x, align 4
28  %0 = atomicrmw add ptr %x, i32 1 seq_cst
29  %add.i = add nsw i32 %0, 2
30  %1 = load volatile i32, ptr %x, align 4
31  %call1 = call i32 (ptr, ...) @printf(ptr @.str, i32 %add.i, i32 %1) nounwind
32  %pair = cmpxchg ptr %x, i32 1, i32 2 seq_cst seq_cst
33  %2 = extractvalue { i32, i1 } %pair, 0
34  %3 = load volatile i32, ptr %x, align 4
35  %call2 = call i32 (ptr, ...) @printf(ptr @.str, i32 %2, i32 %3) nounwind
36  %4 = atomicrmw xchg ptr %x, i32 1 seq_cst
37  %5 = load volatile i32, ptr %x, align 4
38  %call3 = call i32 (ptr, ...) @printf(ptr @.str, i32 %4, i32 %5) nounwind
39; 16-LABEL: main:
40; 16:	lw	${{[0-9]+}}, %call16(__sync_synchronize)(${{[0-9]+}})
41; 16: 	lw	${{[0-9]+}}, %call16(__sync_fetch_and_add_4)(${{[0-9]+}})
42; 16:	lw	${{[0-9]+}}, %call16(__sync_val_compare_and_swap_4)(${{[0-9]+}})
43; 16:	lw	${{[0-9]+}}, %call16(__sync_lock_test_and_set_4)(${{[0-9]+}})
44
45  ret i32 0
46}
47
48declare i32 @printf(ptr nocapture, ...) nounwind
49