xref: /llvm-project/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll (revision 373c343a77a7afaa07179db1754a52b620dfaf2e) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc  -O0 -mtriple=mipsel-linux-gnu -global-isel  -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
3define i32 @mul_i32(i32 %x, i32 %y) {
4; MIPS32-LABEL: mul_i32:
5; MIPS32:       # %bb.0: # %entry
6; MIPS32-NEXT:    mul $2, $4, $5
7; MIPS32-NEXT:    jr $ra
8; MIPS32-NEXT:    nop
9entry:
10  %z = mul i32 %x, %y
11  ret i32 %z
12}
13
14define signext i8 @mul_i8_sext(i8 signext %a, i8 signext %b) {
15; MIPS32-LABEL: mul_i8_sext:
16; MIPS32:       # %bb.0: # %entry
17; MIPS32-NEXT:    mul $1, $5, $4
18; MIPS32-NEXT:    sll $1, $1, 24
19; MIPS32-NEXT:    sra $2, $1, 24
20; MIPS32-NEXT:    jr $ra
21; MIPS32-NEXT:    nop
22entry:
23  %mul = mul i8 %b, %a
24  ret i8 %mul
25}
26
27define zeroext i8 @mul_i8_zext(i8 zeroext %a, i8 zeroext %b) {
28; MIPS32-LABEL: mul_i8_zext:
29; MIPS32:       # %bb.0: # %entry
30; MIPS32-NEXT:    mul $1, $5, $4
31; MIPS32-NEXT:    andi $2, $1, 255
32; MIPS32-NEXT:    jr $ra
33; MIPS32-NEXT:    nop
34entry:
35  %mul = mul i8 %b, %a
36  ret i8 %mul
37}
38
39define i8 @mul_i8_aext(i8 %a, i8 %b) {
40; MIPS32-LABEL: mul_i8_aext:
41; MIPS32:       # %bb.0: # %entry
42; MIPS32-NEXT:    mul $2, $5, $4
43; MIPS32-NEXT:    jr $ra
44; MIPS32-NEXT:    nop
45entry:
46  %mul = mul i8 %b, %a
47  ret i8 %mul
48}
49
50define signext i16 @mul_i16_sext(i16 signext %a, i16 signext %b) {
51; MIPS32-LABEL: mul_i16_sext:
52; MIPS32:       # %bb.0: # %entry
53; MIPS32-NEXT:    mul $1, $5, $4
54; MIPS32-NEXT:    sll $1, $1, 16
55; MIPS32-NEXT:    sra $2, $1, 16
56; MIPS32-NEXT:    jr $ra
57; MIPS32-NEXT:    nop
58entry:
59  %mul = mul i16 %b, %a
60  ret i16 %mul
61}
62
63define zeroext i16 @mul_i16_zext(i16 zeroext %a, i16 zeroext %b) {
64; MIPS32-LABEL: mul_i16_zext:
65; MIPS32:       # %bb.0: # %entry
66; MIPS32-NEXT:    mul $1, $5, $4
67; MIPS32-NEXT:    andi $2, $1, 65535
68; MIPS32-NEXT:    jr $ra
69; MIPS32-NEXT:    nop
70entry:
71  %mul = mul i16 %b, %a
72  ret i16 %mul
73}
74
75define i16 @mul_i16_aext(i16 %a, i16 %b) {
76; MIPS32-LABEL: mul_i16_aext:
77; MIPS32:       # %bb.0: # %entry
78; MIPS32-NEXT:    mul $2, $5, $4
79; MIPS32-NEXT:    jr $ra
80; MIPS32-NEXT:    nop
81entry:
82  %mul = mul i16 %b, %a
83  ret i16 %mul
84}
85
86define i64 @mul_i64(i64 %a, i64 %b) {
87; MIPS32-LABEL: mul_i64:
88; MIPS32:       # %bb.0: # %entry
89; MIPS32-NEXT:    move $3, $4
90; MIPS32-NEXT:    mul $2, $6, $3
91; MIPS32-NEXT:    mul $1, $7, $3
92; MIPS32-NEXT:    mul $4, $6, $5
93; MIPS32-NEXT:    multu $6, $3
94; MIPS32-NEXT:    mfhi $3
95; MIPS32-NEXT:    addu $1, $1, $4
96; MIPS32-NEXT:    addu $3, $1, $3
97; MIPS32-NEXT:    jr $ra
98; MIPS32-NEXT:    nop
99entry:
100  %mul = mul i64 %b, %a
101  ret i64 %mul
102}
103
104define i128 @mul_i128(i128 %a, i128 %b) {
105; MIPS32-LABEL: mul_i128:
106; MIPS32:       # %bb.0: # %entry
107; MIPS32-NEXT:    move $14, $4
108; MIPS32-NEXT:    move $13, $5
109; MIPS32-NEXT:    move $12, $6
110; MIPS32-NEXT:    move $9, $7
111; MIPS32-NEXT:    addiu $1, $sp, 16
112; MIPS32-NEXT:    lw $6, 0($1)
113; MIPS32-NEXT:    addiu $1, $sp, 20
114; MIPS32-NEXT:    lw $7, 0($1)
115; MIPS32-NEXT:    addiu $1, $sp, 24
116; MIPS32-NEXT:    lw $8, 0($1)
117; MIPS32-NEXT:    addiu $1, $sp, 28
118; MIPS32-NEXT:    lw $1, 0($1)
119; MIPS32-NEXT:    mul $2, $6, $14
120; MIPS32-NEXT:    mul $3, $7, $14
121; MIPS32-NEXT:    mul $4, $6, $13
122; MIPS32-NEXT:    multu $6, $14
123; MIPS32-NEXT:    mfhi $5
124; MIPS32-NEXT:    addu $3, $3, $4
125; MIPS32-NEXT:    sltu $4, $3, $4
126; MIPS32-NEXT:    addu $3, $3, $5
127; MIPS32-NEXT:    sltu $5, $3, $5
128; MIPS32-NEXT:    addu $10, $4, $5
129; MIPS32-NEXT:    mul $4, $8, $14
130; MIPS32-NEXT:    mul $5, $7, $13
131; MIPS32-NEXT:    mul $24, $6, $12
132; MIPS32-NEXT:    multu $7, $14
133; MIPS32-NEXT:    mfhi $15
134; MIPS32-NEXT:    multu $6, $13
135; MIPS32-NEXT:    mfhi $11
136; MIPS32-NEXT:    addu $4, $4, $5
137; MIPS32-NEXT:    sltu $5, $4, $5
138; MIPS32-NEXT:    addu $4, $4, $24
139; MIPS32-NEXT:    sltu $24, $4, $24
140; MIPS32-NEXT:    addu $5, $5, $24
141; MIPS32-NEXT:    addu $4, $4, $15
142; MIPS32-NEXT:    sltu $15, $4, $15
143; MIPS32-NEXT:    addu $5, $5, $15
144; MIPS32-NEXT:    addu $4, $4, $11
145; MIPS32-NEXT:    sltu $11, $4, $11
146; MIPS32-NEXT:    addu $5, $5, $11
147; MIPS32-NEXT:    addu $4, $4, $10
148; MIPS32-NEXT:    sltu $10, $4, $10
149; MIPS32-NEXT:    addu $5, $5, $10
150; MIPS32-NEXT:    mul $1, $1, $14
151; MIPS32-NEXT:    mul $11, $8, $13
152; MIPS32-NEXT:    mul $10, $7, $12
153; MIPS32-NEXT:    mul $9, $6, $9
154; MIPS32-NEXT:    multu $8, $14
155; MIPS32-NEXT:    mfhi $8
156; MIPS32-NEXT:    multu $7, $13
157; MIPS32-NEXT:    mfhi $7
158; MIPS32-NEXT:    multu $6, $12
159; MIPS32-NEXT:    mfhi $6
160; MIPS32-NEXT:    addu $1, $1, $11
161; MIPS32-NEXT:    addu $1, $1, $10
162; MIPS32-NEXT:    addu $1, $1, $9
163; MIPS32-NEXT:    addu $1, $1, $8
164; MIPS32-NEXT:    addu $1, $1, $7
165; MIPS32-NEXT:    addu $1, $1, $6
166; MIPS32-NEXT:    addu $5, $1, $5
167; MIPS32-NEXT:    jr $ra
168; MIPS32-NEXT:    nop
169entry:
170  %mul = mul i128 %b, %a
171  ret i128 %mul
172}
173
174declare { i32, i1 } @llvm.umul.with.overflow.i32(i32, i32)
175define void @umul_with_overflow(i32 %lhs, i32 %rhs, ptr %pmul, ptr %pcarry_flag) {
176; MIPS32-LABEL: umul_with_overflow:
177; MIPS32:       # %bb.0:
178; MIPS32-NEXT:    multu $4, $5
179; MIPS32-NEXT:    mfhi $2
180; MIPS32-NEXT:    mul $1, $4, $5
181; MIPS32-NEXT:    sltu $2, $zero, $2
182; MIPS32-NEXT:    andi $2, $2, 1
183; MIPS32-NEXT:    sb $2, 0($7)
184; MIPS32-NEXT:    sw $1, 0($6)
185; MIPS32-NEXT:    jr $ra
186; MIPS32-NEXT:    nop
187  %res = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %lhs, i32 %rhs)
188  %carry_flag = extractvalue { i32, i1 } %res, 1
189  %mul = extractvalue { i32, i1 } %res, 0
190  store i1 %carry_flag, ptr %pcarry_flag
191  store i32 %mul, ptr %pmul
192  ret void
193}
194