1; RUN: llc -mtriple=m68k -mattr="+reserve-a0" < %s | FileCheck --check-prefix=A0 %s 2; RUN: llc -mtriple=m68k -mattr="+reserve-a1" < %s | FileCheck --check-prefix=A1 %s 3; RUN: llc -mtriple=m68k -mattr="+reserve-a2" < %s | FileCheck --check-prefix=A2 %s 4; RUN: llc -mtriple=m68k -mattr="+reserve-a3" < %s | FileCheck --check-prefix=A3 %s 5; RUN: llc -mtriple=m68k -mattr="+reserve-a4" < %s | FileCheck --check-prefix=A4 %s 6; RUN: llc -mtriple=m68k -mattr="+reserve-a5" < %s | FileCheck --check-prefix=A5 %s 7; RUN: llc -mtriple=m68k -mattr="+reserve-a6" < %s | FileCheck --check-prefix=A6 %s 8; RUN: llc -mtriple=m68k -mattr="+reserve-d0" < %s | FileCheck --check-prefix=D0 %s 9; RUN: llc -mtriple=m68k -mattr="+reserve-d1" < %s | FileCheck --check-prefix=D1 %s 10; RUN: llc -mtriple=m68k -mattr="+reserve-d2" < %s | FileCheck --check-prefix=D2 %s 11; RUN: llc -mtriple=m68k -mattr="+reserve-d3" < %s | FileCheck --check-prefix=D3 %s 12; RUN: llc -mtriple=m68k -mattr="+reserve-d4" < %s | FileCheck --check-prefix=D4 %s 13; RUN: llc -mtriple=m68k -mattr="+reserve-d5" < %s | FileCheck --check-prefix=D5 %s 14; RUN: llc -mtriple=m68k -mattr="+reserve-d6" < %s | FileCheck --check-prefix=D6 %s 15; RUN: llc -mtriple=m68k -mattr="+reserve-d7" < %s | FileCheck --check-prefix=D7 %s 16 17; Used to exhaust all registers 18; 19; A better way to do this might be: 20; ``` 21; @var = global [16 x i32] zeroinitializer 22; ... 23; %tmp = load load volatile [16 x i32], [16 x i32]* @var 24; store volatile [16 x i32] %tmp, [16 x i32]* @var 25; ``` 26; Which is copied from `test/CodeGen/RISCV/reserved-regs.ll`. 27; But currently we have problem doing codegen for the above snippet 28; (https://bugs.llvm.org/show_bug.cgi?id=50377). 29define void @foo(ptr nocapture readonly %a, ptr nocapture readonly %b, ptr nocapture readonly %c, ptr nocapture readonly %d, 30 ptr nocapture readonly %a1, ptr nocapture readonly %b1, ptr nocapture readonly %c1, ptr nocapture readonly %d1, 31 ptr nocapture readonly %a2, ptr nocapture readonly %b2, ptr nocapture readonly %c2, ptr nocapture readonly %d2, 32 ptr nocapture readonly %a3, ptr nocapture readonly %b3, ptr nocapture readonly %c3, ptr nocapture readonly %d3) { 33entry: 34 %0 = load i32, ptr %a, align 4 35 %1 = load i32, ptr %b, align 4 36 %2 = load i32, ptr %c, align 4 37 %3 = load i32, ptr %d, align 4 38 %4 = load i32, ptr %a1, align 4 39 %5 = load i32, ptr %b1, align 4 40 %6 = load i32, ptr %c1, align 4 41 %7 = load i32, ptr %d1, align 4 42 %8 = load i32, ptr %a2, align 4 43 %9 = load i32, ptr %b2, align 4 44 %10 = load i32, ptr %c2, align 4 45 %11 = load i32, ptr %d2, align 4 46 %12 = load i32, ptr %a3, align 4 47 %13 = load i32, ptr %b3, align 4 48 %14 = load i32, ptr %c3, align 4 49 %15 = load i32, ptr %d3, align 4 50 ; A0-NOT: %a0 51 ; A1-NOT: %a1 52 ; A2-NOT: %a2 53 ; A3-NOT: %a3 54 ; A4-NOT: %a4 55 ; A5-NOT: %a5 56 ; A6-NOT: %a6 57 ; D0-NOT: %d0 58 ; D1-NOT: %d1 59 ; D2-NOT: %d2 60 ; D3-NOT: %d3 61 ; D4-NOT: %d4 62 ; D5-NOT: %d5 63 ; D6-NOT: %d6 64 ; D7-NOT: %d7 65 tail call void @bar(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, i32 %8, i32 %9, i32 %10, i32 %11, i32 %12, i32 %13, i32 %14, i32 %15) 66 ret void 67} 68 69declare void @bar(i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) 70 71