1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=m68k-linux -verify-machineinstrs | FileCheck %s 3 4declare i8 @llvm.fshr.i8(i8, i8, i8) 5declare i16 @llvm.fshr.i16(i16, i16, i16) 6declare i32 @llvm.fshr.i32(i32, i32, i32) 7 8; op reg, reg 9 10define zeroext i8 @rorb(i8 zeroext %a, i8 zeroext %b) nounwind { 11; CHECK-LABEL: rorb: 12; CHECK: ; %bb.0: 13; CHECK-NEXT: move.b (11,%sp), %d0 14; CHECK-NEXT: move.b (7,%sp), %d1 15; CHECK-NEXT: ror.b %d0, %d1 16; CHECK-NEXT: move.l %d1, %d0 17; CHECK-NEXT: and.l #255, %d0 18; CHECK-NEXT: rts 19 %1 = tail call i8 @llvm.fshr.i8(i8 %a, i8 %a, i8 %b) 20 ret i8 %1 21} 22 23define zeroext i16 @rorw(i16 zeroext %a, i16 zeroext %b) nounwind { 24; CHECK-LABEL: rorw: 25; CHECK: ; %bb.0: 26; CHECK-NEXT: move.w (10,%sp), %d0 27; CHECK-NEXT: move.w (6,%sp), %d1 28; CHECK-NEXT: ror.w %d0, %d1 29; CHECK-NEXT: move.l %d1, %d0 30; CHECK-NEXT: and.l #65535, %d0 31; CHECK-NEXT: rts 32 %1 = tail call i16 @llvm.fshr.i16(i16 %a, i16 %a, i16 %b) 33 ret i16 %1 34} 35 36define i32 @rorl(i32 %a, i32 %b) nounwind { 37; CHECK-LABEL: rorl: 38; CHECK: ; %bb.0: 39; CHECK-NEXT: move.l (8,%sp), %d1 40; CHECK-NEXT: move.l (4,%sp), %d0 41; CHECK-NEXT: ror.l %d1, %d0 42; CHECK-NEXT: rts 43 %1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %b) 44 ret i32 %1 45} 46 47; op reg, imm 48 49define zeroext i8 @rorib(i8 zeroext %a) nounwind { 50; CHECK-LABEL: rorib: 51; CHECK: ; %bb.0: 52; CHECK-NEXT: move.b (7,%sp), %d0 53; CHECK-NEXT: ror.b #3, %d0 54; CHECK-NEXT: and.l #255, %d0 55; CHECK-NEXT: rts 56 %1 = tail call i8 @llvm.fshr.i8(i8 %a, i8 %a, i8 3) 57 ret i8 %1 58} 59 60define zeroext i16 @roriw(i16 zeroext %a) nounwind { 61; CHECK-LABEL: roriw: 62; CHECK: ; %bb.0: 63; CHECK-NEXT: move.w (6,%sp), %d0 64; CHECK-NEXT: ror.w #5, %d0 65; CHECK-NEXT: and.l #65535, %d0 66; CHECK-NEXT: rts 67 %1 = tail call i16 @llvm.fshr.i16(i16 %a, i16 %a, i16 5) 68 ret i16 %1 69} 70 71define i32 @roril(i32 %a) nounwind { 72; CHECK-LABEL: roril: 73; CHECK: ; %bb.0: 74; CHECK-NEXT: move.l (4,%sp), %d0 75; CHECK-NEXT: ror.l #7, %d0 76; CHECK-NEXT: rts 77 %1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 7) 78 ret i32 %1 79} 80