xref: /llvm-project/llvm/test/CodeGen/M68k/Control/cmp.ll (revision c4c9d4f306732c854fa88d2f30c1a22bb025d0c9) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=m68k -verify-machineinstrs | FileCheck %s
3
4define i32 @test1(ptr %y) nounwind {
5; CHECK-LABEL: test1:
6; CHECK:       ; %bb.0:
7; CHECK-NEXT:    move.l (4,%sp), %a0
8; CHECK-NEXT:    cmpi.l #0, (%a0)
9; CHECK-NEXT:    beq .LBB0_2
10; CHECK-NEXT:  ; %bb.1: ; %cond_false
11; CHECK-NEXT:    moveq #0, %d0
12; CHECK-NEXT:    rts
13; CHECK-NEXT:  .LBB0_2: ; %cond_true
14; CHECK-NEXT:    moveq #1, %d0
15; CHECK-NEXT:    rts
16 %tmp = load i32, ptr %y  ; <i32> [#uses=1]
17 %tmp.upgrd.1 = icmp eq i32 %tmp, 0  ; <i1> [#uses=1]
18 br i1 %tmp.upgrd.1, label %cond_true, label %cond_false
19
20cond_false:  ; preds = %0
21 ret i32 0
22
23cond_true:     ; preds = %0
24 ret i32 1
25}
26
27define i32 @test2(ptr %y) nounwind {
28; CHECK-LABEL: test2:
29; CHECK:       ; %bb.0:
30; CHECK-NEXT:    move.l (4,%sp), %a0
31; CHECK-NEXT:    move.l (%a0), %d0
32; CHECK-NEXT:    and.l #536870911, %d0
33; CHECK-NEXT:    cmpi.l #0, %d0
34; CHECK-NEXT:    beq .LBB1_2
35; CHECK-NEXT:  ; %bb.1: ; %cond_false
36; CHECK-NEXT:    moveq #0, %d0
37; CHECK-NEXT:    rts
38; CHECK-NEXT:  .LBB1_2: ; %cond_true
39; CHECK-NEXT:    moveq #1, %d0
40; CHECK-NEXT:    rts
41 %tmp = load i32, ptr %y  ; <i32> [#uses=1]
42 %tmp1 = shl i32 %tmp, 3  ; <i32> [#uses=1]
43 %tmp1.upgrd.2 = icmp eq i32 %tmp1, 0  ; <i1> [#uses=1]
44 br i1 %tmp1.upgrd.2, label %cond_true, label %cond_false
45
46cond_false:  ; preds = %0
47 ret i32 0
48
49cond_true:  ; preds = %0
50 ret i32 1
51}
52
53define i8 @test2b(ptr %y) nounwind {
54; CHECK-LABEL: test2b:
55; CHECK:       ; %bb.0:
56; CHECK-NEXT:    move.l (4,%sp), %a0
57; CHECK-NEXT:    move.b (%a0), %d0
58; CHECK-NEXT:    and.b #31, %d0
59; CHECK-NEXT:    cmpi.b #0, %d0
60; CHECK-NEXT:    beq .LBB2_2
61; CHECK-NEXT:  ; %bb.1: ; %cond_false
62; CHECK-NEXT:    moveq #0, %d0
63; CHECK-NEXT:    rts
64; CHECK-NEXT:  .LBB2_2: ; %cond_true
65; CHECK-NEXT:    moveq #1, %d0
66; CHECK-NEXT:    rts
67 %tmp = load i8, ptr %y  ; <i8> [#uses=1]
68 %tmp1 = shl i8 %tmp, 3  ; <i8> [#uses=1]
69 %tmp1.upgrd.2 = icmp eq i8 %tmp1, 0  ; <i1> [#uses=1]
70 br i1 %tmp1.upgrd.2, label %cond_true, label %cond_false
71
72cond_false:  ; preds = %0
73 ret i8 0
74
75cond_true:  ; preds = %0
76 ret i8 1
77}
78
79define i64 @test3(i64 %x) nounwind {
80; CHECK-LABEL: test3:
81; CHECK:       ; %bb.0:
82; CHECK-NEXT:    move.l (8,%sp), %d0
83; CHECK-NEXT:    or.l (4,%sp), %d0
84; CHECK-NEXT:    seq %d0
85; CHECK-NEXT:    move.l %d0, %d1
86; CHECK-NEXT:    and.l #255, %d1
87; CHECK-NEXT:    moveq #0, %d0
88; CHECK-NEXT:    rts
89  %t = icmp eq i64 %x, 0
90  %r = zext i1 %t to i64
91  ret i64 %r
92}
93
94define i64 @test4(i64 %x) nounwind {
95; CHECK-LABEL: test4:
96; CHECK:       ; %bb.0:
97; CHECK-NEXT:    suba.l #4, %sp
98; CHECK-NEXT:    movem.l %d2, (0,%sp) ; 8-byte Folded Spill
99; CHECK-NEXT:    move.l (8,%sp), %d1
100; CHECK-NEXT:    moveq #0, %d0
101; CHECK-NEXT:    move.l (12,%sp), %d2
102; CHECK-NEXT:    sub.l #1, %d2
103; CHECK-NEXT:    subx.l %d0, %d1
104; CHECK-NEXT:    slt %d1
105; CHECK-NEXT:    and.l #255, %d1
106; CHECK-NEXT:    movem.l (0,%sp), %d2 ; 8-byte Folded Reload
107; CHECK-NEXT:    adda.l #4, %sp
108; CHECK-NEXT:    rts
109  %t = icmp slt i64 %x, 1
110  %r = zext i1 %t to i64
111  ret i64 %r
112}
113
114define i32 @test6() nounwind align 2 {
115; CHECK-LABEL: test6:
116; CHECK:       ; %bb.0:
117; CHECK-NEXT:    suba.l #20, %sp
118; CHECK-NEXT:    move.l (12,%sp), %d0
119; CHECK-NEXT:    or.l (8,%sp), %d0
120; CHECK-NEXT:    beq .LBB5_1
121; CHECK-NEXT:  ; %bb.2: ; %F
122; CHECK-NEXT:    moveq #0, %d0
123; CHECK-NEXT:    adda.l #20, %sp
124; CHECK-NEXT:    rts
125; CHECK-NEXT:  .LBB5_1: ; %T
126; CHECK-NEXT:    moveq #1, %d0
127; CHECK-NEXT:    adda.l #20, %sp
128; CHECK-NEXT:    rts
129  %A = alloca {i64, i64}, align 8
130  %B = getelementptr inbounds {i64, i64}, ptr %A, i64 0, i32 1
131  %C = load i64, ptr %B
132  %D = icmp eq i64 %C, 0
133  br i1 %D, label %T, label %F
134T:
135  ret i32 1
136
137F:
138  ret i32 0
139}
140
141define i32 @test7(i64 %res) nounwind {
142; CHECK-LABEL: test7:
143; CHECK:       ; %bb.0: ; %entry
144; CHECK-NEXT:    cmpi.l #0, (4,%sp)
145; CHECK-NEXT:    seq %d0
146; CHECK-NEXT:    and.l #255, %d0
147; CHECK-NEXT:    rts
148entry:
149  %lnot = icmp ult i64 %res, 4294967296
150  %lnot.ext = zext i1 %lnot to i32
151  ret i32 %lnot.ext
152}
153
154define i32 @test8(i64 %res) nounwind {
155; CHECK-LABEL: test8:
156; CHECK:       ; %bb.0: ; %entry
157; CHECK-NEXT:    move.l (4,%sp), %d0
158; CHECK-NEXT:    sub.l #3, %d0
159; CHECK-NEXT:    scs %d0
160; CHECK-NEXT:    and.l #255, %d0
161; CHECK-NEXT:    rts
162entry:
163  %lnot = icmp ult i64 %res, 12884901888
164  %lnot.ext = zext i1 %lnot to i32
165  ret i32 %lnot.ext
166}
167
168define i32 @test11(i64 %l) nounwind {
169; CHECK-LABEL: test11:
170; CHECK:       ; %bb.0: ; %entry
171; CHECK-NEXT:    move.l (4,%sp), %d0
172; CHECK-NEXT:    and.l #-32768, %d0
173; CHECK-NEXT:    sub.l #32768, %d0
174; CHECK-NEXT:    seq %d0
175; CHECK-NEXT:    and.l #255, %d0
176; CHECK-NEXT:    rts
177entry:
178  %shr.mask = and i64 %l, -140737488355328
179  %cmp = icmp eq i64 %shr.mask, 140737488355328
180  %conv = zext i1 %cmp to i32
181  ret i32 %conv
182}
183
184define i32 @test13(i32 %mask, i32 %base, i32 %intra) {
185; CHECK-LABEL: test13:
186; CHECK:         .cfi_startproc
187; CHECK-NEXT:  ; %bb.0:
188; CHECK-NEXT:    move.b (7,%sp), %d0
189; CHECK-NEXT:    and.b #8, %d0
190; CHECK-NEXT:    cmpi.b #0, %d0
191; CHECK-NEXT:    bne .LBB9_1
192; CHECK-NEXT:  ; %bb.2:
193; CHECK-NEXT:    lea (8,%sp), %a0
194; CHECK-NEXT:    move.l (%a0), %d0
195; CHECK-NEXT:    rts
196; CHECK-NEXT:  .LBB9_1:
197; CHECK-NEXT:    lea (12,%sp), %a0
198; CHECK-NEXT:    move.l (%a0), %d0
199; CHECK-NEXT:    rts
200  %and = and i32 %mask, 8
201  %tobool = icmp ne i32 %and, 0
202  %cond = select i1 %tobool, i32 %intra, i32 %base
203  ret i32 %cond
204}
205
206define i32 @test14(i32 %mask, i32 %base, i32 %intra) #0 {
207; CHECK-LABEL: test14:
208; CHECK:         .cfi_startproc
209; CHECK-NEXT:  ; %bb.0:
210; CHECK-NEXT:    move.l (4,%sp), %d0
211; CHECK-NEXT:    lsr.l #7, %d0
212; CHECK-NEXT:    cmpi.l #0, %d0
213; CHECK-NEXT:    bpl .LBB10_1
214; CHECK-NEXT:  ; %bb.2:
215; CHECK-NEXT:    lea (8,%sp), %a0
216; CHECK-NEXT:    move.l (%a0), %d0
217; CHECK-NEXT:    rts
218; CHECK-NEXT:  .LBB10_1:
219; CHECK-NEXT:    lea (12,%sp), %a0
220; CHECK-NEXT:    move.l (%a0), %d0
221; CHECK-NEXT:    rts
222  %s = lshr i32 %mask, 7
223  %tobool = icmp sgt i32 %s, -1
224  %cond = select i1 %tobool, i32 %intra, i32 %base
225  ret i32 %cond
226}
227
228define zeroext i1 @test15(i32 %bf.load, i32 %n) {
229; CHECK-LABEL: test15:
230; CHECK:         .cfi_startproc
231; CHECK-NEXT:  ; %bb.0:
232; CHECK-NEXT:    moveq #16, %d0
233; CHECK-NEXT:    move.l (4,%sp), %d1
234; CHECK-NEXT:    lsr.l %d0, %d1
235; CHECK-NEXT:    move.l %d1, %d0
236; CHECK-NEXT:    sub.l (8,%sp), %d0
237; CHECK-NEXT:    scc %d0
238; CHECK-NEXT:    cmpi.l #0, %d1
239; CHECK-NEXT:    seq %d1
240; CHECK-NEXT:    or.b %d0, %d1
241; CHECK-NEXT:    move.l %d1, %d0
242; CHECK-NEXT:    and.l #255, %d0
243; CHECK-NEXT:    rts
244  %bf.lshr = lshr i32 %bf.load, 16
245  %cmp2 = icmp eq i32 %bf.lshr, 0
246  %cmp5 = icmp uge i32 %bf.lshr, %n
247  %.cmp5 = or i1 %cmp2, %cmp5
248  ret i1 %.cmp5
249}
250
251define i8 @test16(i16 signext %L) {
252; CHECK-LABEL: test16:
253; CHECK:         .cfi_startproc
254; CHECK-NEXT:  ; %bb.0:
255; CHECK-NEXT:    moveq #15, %d1
256; CHECK-NEXT:    move.w (6,%sp), %d0
257; CHECK-NEXT:    lsr.w %d1, %d0
258; CHECK-NEXT:    eori.b #1, %d0
259; CHECK-NEXT:    ; kill: def $bd0 killed $bd0 killed $wd0
260; CHECK-NEXT:    rts
261  %lshr  = lshr i16 %L, 15
262  %trunc = trunc i16 %lshr to i8
263  %not   = xor i8 %trunc, 1
264  ret i8 %not
265}
266
267define i8 @test18(i64 %L) {
268; CHECK-LABEL: test18:
269; CHECK:         .cfi_startproc
270; CHECK-NEXT:  ; %bb.0:
271; CHECK-NEXT:    moveq #31, %d1
272; CHECK-NEXT:    move.l (4,%sp), %d0
273; CHECK-NEXT:    lsr.l %d1, %d0
274; CHECK-NEXT:    eori.b #1, %d0
275; CHECK-NEXT:    ; kill: def $bd0 killed $bd0 killed $d0
276; CHECK-NEXT:    rts
277  %lshr  = lshr i64 %L, 63
278  %trunc = trunc i64 %lshr to i8
279  %not   = xor i8 %trunc, 1
280  ret i8 %not
281}
282
283@d = global i8 0, align 1
284
285define void @test20(i32 %bf.load, i8 %x1, ptr %b_addr) {
286; CHECK-LABEL: test20:
287; CHECK:         .cfi_startproc
288; CHECK-NEXT:  ; %bb.0:
289; CHECK-NEXT:    suba.l #4, %sp
290; CHECK-NEXT:    .cfi_def_cfa_offset -8
291; CHECK-NEXT:    movem.l %d2, (0,%sp) ; 8-byte Folded Spill
292; CHECK-NEXT:    move.l #16777215, %d0
293; CHECK-NEXT:    and.l (8,%sp), %d0
294; CHECK-NEXT:    sne %d1
295; CHECK-NEXT:    and.l #255, %d1
296; CHECK-NEXT:    move.l (16,%sp), %a0
297; CHECK-NEXT:    move.b (15,%sp), %d2
298; CHECK-NEXT:    and.l #255, %d2
299; CHECK-NEXT:    add.l %d1, %d2
300; CHECK-NEXT:    sne (%a0)
301; CHECK-NEXT:    cmpi.l #0, %d0
302; CHECK-NEXT:    lea (d,%pc), %a0
303; CHECK-NEXT:    sne (%a0)
304; CHECK-NEXT:    movem.l (0,%sp), %d2 ; 8-byte Folded Reload
305; CHECK-NEXT:    adda.l #4, %sp
306; CHECK-NEXT:    rts
307  %bf.shl = shl i32 %bf.load, 8
308  %bf.ashr = ashr exact i32 %bf.shl, 8
309  %tobool4 = icmp ne i32 %bf.ashr, 0
310  %conv = zext i1 %tobool4 to i32
311  %conv6 = zext i8 %x1 to i32
312  %add = add nuw nsw i32 %conv, %conv6
313  %tobool7 = icmp ne i32 %add, 0
314  %frombool = zext i1 %tobool7 to i8
315  store i8 %frombool, ptr %b_addr, align 1
316  %tobool14 = icmp ne i32 %bf.shl, 0
317  %frombool15 = zext i1 %tobool14 to i8
318  store i8 %frombool15, ptr @d, align 1
319  ret void
320}
321