xref: /llvm-project/llvm/test/CodeGen/M68k/CConv/rtd-ret.ll (revision fd84b1a99dfe37d4212be8afba2a93209679bc7f)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2; RUN: llc -mtriple=m68k < %s | FileCheck %s
3
4define dso_local m68k_rtdcc i32 @ret(i32 noundef %a, i32 noundef %b, i32 noundef %c) nounwind {
5; CHECK-LABEL: ret:
6; CHECK:       ; %bb.0: ; %entry
7; CHECK-NEXT:    move.l (8,%sp), %d0
8; CHECK-NEXT:    add.l (4,%sp), %d0
9; CHECK-NEXT:    add.l (12,%sp), %d0
10; CHECK-NEXT:    move.l (%sp), %a1
11; CHECK-NEXT:    adda.l #12, %sp
12; CHECK-NEXT:    move.l %a1, (%sp)
13; CHECK-NEXT:    rts
14entry:
15  %add = add nsw i32 %b, %a
16  %add1 = add nsw i32 %add, %c
17  ret i32 %add1
18}
19
20define dso_local m68k_rtdcc i32 @va_ret(i32 noundef %a, i32 noundef %b, i32 noundef %c, ...) nounwind {
21; CHECK-LABEL: va_ret:
22; CHECK:       ; %bb.0: ; %entry
23; CHECK-NEXT:    move.l (8,%sp), %d0
24; CHECK-NEXT:    add.l (4,%sp), %d0
25; CHECK-NEXT:    add.l (12,%sp), %d0
26; CHECK-NEXT:    rts
27entry:
28  %add = add nsw i32 %b, %a
29  %add1 = add nsw i32 %add, %c
30  ret i32 %add1
31}
32