1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 2; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s 3 4define void @mul_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind { 5; CHECK-LABEL: mul_v16i8: 6; CHECK: # %bb.0: # %entry 7; CHECK-NEXT: vld $vr0, $a1, 0 8; CHECK-NEXT: vld $vr1, $a2, 0 9; CHECK-NEXT: vmul.b $vr0, $vr0, $vr1 10; CHECK-NEXT: vst $vr0, $a0, 0 11; CHECK-NEXT: ret 12entry: 13 %v0 = load <16 x i8>, ptr %a0 14 %v1 = load <16 x i8>, ptr %a1 15 %v2 = mul <16 x i8> %v0, %v1 16 store <16 x i8> %v2, ptr %res 17 ret void 18} 19 20define void @mul_v8i16(ptr %res, ptr %a0, ptr %a1) nounwind { 21; CHECK-LABEL: mul_v8i16: 22; CHECK: # %bb.0: # %entry 23; CHECK-NEXT: vld $vr0, $a1, 0 24; CHECK-NEXT: vld $vr1, $a2, 0 25; CHECK-NEXT: vmul.h $vr0, $vr0, $vr1 26; CHECK-NEXT: vst $vr0, $a0, 0 27; CHECK-NEXT: ret 28entry: 29 %v0 = load <8 x i16>, ptr %a0 30 %v1 = load <8 x i16>, ptr %a1 31 %v2 = mul <8 x i16> %v0, %v1 32 store <8 x i16> %v2, ptr %res 33 ret void 34} 35 36define void @mul_v4i32(ptr %res, ptr %a0, ptr %a1) nounwind { 37; CHECK-LABEL: mul_v4i32: 38; CHECK: # %bb.0: # %entry 39; CHECK-NEXT: vld $vr0, $a1, 0 40; CHECK-NEXT: vld $vr1, $a2, 0 41; CHECK-NEXT: vmul.w $vr0, $vr0, $vr1 42; CHECK-NEXT: vst $vr0, $a0, 0 43; CHECK-NEXT: ret 44entry: 45 %v0 = load <4 x i32>, ptr %a0 46 %v1 = load <4 x i32>, ptr %a1 47 %v2 = mul <4 x i32> %v0, %v1 48 store <4 x i32> %v2, ptr %res 49 ret void 50} 51 52define void @mul_v2i64(ptr %res, ptr %a0, ptr %a1) nounwind { 53; CHECK-LABEL: mul_v2i64: 54; CHECK: # %bb.0: # %entry 55; CHECK-NEXT: vld $vr0, $a1, 0 56; CHECK-NEXT: vld $vr1, $a2, 0 57; CHECK-NEXT: vmul.d $vr0, $vr0, $vr1 58; CHECK-NEXT: vst $vr0, $a0, 0 59; CHECK-NEXT: ret 60entry: 61 %v0 = load <2 x i64>, ptr %a0 62 %v1 = load <2 x i64>, ptr %a1 63 %v2 = mul <2 x i64> %v0, %v1 64 store <2 x i64> %v2, ptr %res 65 ret void 66} 67 68define void @mul_square_v16i8(ptr %res, ptr %a0) nounwind { 69; CHECK-LABEL: mul_square_v16i8: 70; CHECK: # %bb.0: # %entry 71; CHECK-NEXT: vld $vr0, $a1, 0 72; CHECK-NEXT: vmul.b $vr0, $vr0, $vr0 73; CHECK-NEXT: vst $vr0, $a0, 0 74; CHECK-NEXT: ret 75entry: 76 %v0 = load <16 x i8>, ptr %a0 77 %v1 = mul <16 x i8> %v0, %v0 78 store <16 x i8> %v1, ptr %res 79 ret void 80} 81 82define void @mul_square_v8i16(ptr %res, ptr %a0) nounwind { 83; CHECK-LABEL: mul_square_v8i16: 84; CHECK: # %bb.0: # %entry 85; CHECK-NEXT: vld $vr0, $a1, 0 86; CHECK-NEXT: vmul.h $vr0, $vr0, $vr0 87; CHECK-NEXT: vst $vr0, $a0, 0 88; CHECK-NEXT: ret 89entry: 90 %v0 = load <8 x i16>, ptr %a0 91 %v1 = mul <8 x i16> %v0, %v0 92 store <8 x i16> %v1, ptr %res 93 ret void 94} 95 96define void @mul_square_v4i32(ptr %res, ptr %a0) nounwind { 97; CHECK-LABEL: mul_square_v4i32: 98; CHECK: # %bb.0: # %entry 99; CHECK-NEXT: vld $vr0, $a1, 0 100; CHECK-NEXT: vmul.w $vr0, $vr0, $vr0 101; CHECK-NEXT: vst $vr0, $a0, 0 102; CHECK-NEXT: ret 103entry: 104 %v0 = load <4 x i32>, ptr %a0 105 %v1 = mul <4 x i32> %v0, %v0 106 store <4 x i32> %v1, ptr %res 107 ret void 108} 109 110define void @mul_square_v2i64(ptr %res, ptr %a0) nounwind { 111; CHECK-LABEL: mul_square_v2i64: 112; CHECK: # %bb.0: # %entry 113; CHECK-NEXT: vld $vr0, $a1, 0 114; CHECK-NEXT: vmul.d $vr0, $vr0, $vr0 115; CHECK-NEXT: vst $vr0, $a0, 0 116; CHECK-NEXT: ret 117entry: 118 %v0 = load <2 x i64>, ptr %a0 119 %v1 = mul <2 x i64> %v0, %v0 120 store <2 x i64> %v1, ptr %res 121 ret void 122} 123 124define void @mul_v16i8_8(ptr %res, ptr %a0) nounwind { 125; CHECK-LABEL: mul_v16i8_8: 126; CHECK: # %bb.0: # %entry 127; CHECK-NEXT: vld $vr0, $a1, 0 128; CHECK-NEXT: vslli.b $vr0, $vr0, 3 129; CHECK-NEXT: vst $vr0, $a0, 0 130; CHECK-NEXT: ret 131entry: 132 %v0 = load <16 x i8>, ptr %a0 133 %v1 = mul <16 x i8> %v0, <i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8> 134 store <16 x i8> %v1, ptr %res 135 ret void 136} 137 138define void @mul_v8i16_8(ptr %res, ptr %a0) nounwind { 139; CHECK-LABEL: mul_v8i16_8: 140; CHECK: # %bb.0: # %entry 141; CHECK-NEXT: vld $vr0, $a1, 0 142; CHECK-NEXT: vslli.h $vr0, $vr0, 3 143; CHECK-NEXT: vst $vr0, $a0, 0 144; CHECK-NEXT: ret 145entry: 146 %v0 = load <8 x i16>, ptr %a0 147 %v1 = mul <8 x i16> %v0, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8> 148 store <8 x i16> %v1, ptr %res 149 ret void 150} 151 152define void @mul_v4i32_8(ptr %res, ptr %a0) nounwind { 153; CHECK-LABEL: mul_v4i32_8: 154; CHECK: # %bb.0: # %entry 155; CHECK-NEXT: vld $vr0, $a1, 0 156; CHECK-NEXT: vslli.w $vr0, $vr0, 3 157; CHECK-NEXT: vst $vr0, $a0, 0 158; CHECK-NEXT: ret 159entry: 160 %v0 = load <4 x i32>, ptr %a0 161 %v1 = mul <4 x i32> %v0, <i32 8, i32 8, i32 8, i32 8> 162 store <4 x i32> %v1, ptr %res 163 ret void 164} 165 166define void @mul_v2i64_8(ptr %res, ptr %a0) nounwind { 167; CHECK-LABEL: mul_v2i64_8: 168; CHECK: # %bb.0: # %entry 169; CHECK-NEXT: vld $vr0, $a1, 0 170; CHECK-NEXT: vslli.d $vr0, $vr0, 3 171; CHECK-NEXT: vst $vr0, $a0, 0 172; CHECK-NEXT: ret 173entry: 174 %v0 = load <2 x i64>, ptr %a0 175 %v1 = mul <2 x i64> %v0, <i64 8, i64 8> 176 store <2 x i64> %v1, ptr %res 177 ret void 178} 179 180define void @mul_v16i8_17(ptr %res, ptr %a0) nounwind { 181; CHECK-LABEL: mul_v16i8_17: 182; CHECK: # %bb.0: # %entry 183; CHECK-NEXT: vld $vr0, $a1, 0 184; CHECK-NEXT: vrepli.b $vr1, 17 185; CHECK-NEXT: vmul.b $vr0, $vr0, $vr1 186; CHECK-NEXT: vst $vr0, $a0, 0 187; CHECK-NEXT: ret 188entry: 189 %v0 = load <16 x i8>, ptr %a0 190 %v1 = mul <16 x i8> %v0, <i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17> 191 store <16 x i8> %v1, ptr %res 192 ret void 193} 194 195define void @mul_v8i16_17(ptr %res, ptr %a0) nounwind { 196; CHECK-LABEL: mul_v8i16_17: 197; CHECK: # %bb.0: # %entry 198; CHECK-NEXT: vld $vr0, $a1, 0 199; CHECK-NEXT: vrepli.h $vr1, 17 200; CHECK-NEXT: vmul.h $vr0, $vr0, $vr1 201; CHECK-NEXT: vst $vr0, $a0, 0 202; CHECK-NEXT: ret 203entry: 204 %v0 = load <8 x i16>, ptr %a0 205 %v1 = mul <8 x i16> %v0, <i16 17, i16 17, i16 17, i16 17, i16 17, i16 17, i16 17, i16 17> 206 store <8 x i16> %v1, ptr %res 207 ret void 208} 209 210define void @mul_v4i32_17(ptr %res, ptr %a0) nounwind { 211; CHECK-LABEL: mul_v4i32_17: 212; CHECK: # %bb.0: # %entry 213; CHECK-NEXT: vld $vr0, $a1, 0 214; CHECK-NEXT: vrepli.w $vr1, 17 215; CHECK-NEXT: vmul.w $vr0, $vr0, $vr1 216; CHECK-NEXT: vst $vr0, $a0, 0 217; CHECK-NEXT: ret 218entry: 219 %v0 = load <4 x i32>, ptr %a0 220 %v1 = mul <4 x i32> %v0, <i32 17, i32 17, i32 17, i32 17> 221 store <4 x i32> %v1, ptr %res 222 ret void 223} 224 225define void @mul_v2i64_17(ptr %res, ptr %a0) nounwind { 226; CHECK-LABEL: mul_v2i64_17: 227; CHECK: # %bb.0: # %entry 228; CHECK-NEXT: vld $vr0, $a1, 0 229; CHECK-NEXT: vrepli.d $vr1, 17 230; CHECK-NEXT: vmul.d $vr0, $vr0, $vr1 231; CHECK-NEXT: vst $vr0, $a0, 0 232; CHECK-NEXT: ret 233entry: 234 %v0 = load <2 x i64>, ptr %a0 235 %v1 = mul <2 x i64> %v0, <i64 17, i64 17> 236 store <2 x i64> %v1, ptr %res 237 ret void 238} 239