1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 2; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s 3 4define void @insert_16xi8(ptr %src, ptr %dst, i8 %ins) nounwind { 5; CHECK-LABEL: insert_16xi8: 6; CHECK: # %bb.0: 7; CHECK-NEXT: vld $vr0, $a0, 0 8; CHECK-NEXT: vinsgr2vr.b $vr0, $a2, 1 9; CHECK-NEXT: vst $vr0, $a1, 0 10; CHECK-NEXT: ret 11 %v = load volatile <16 x i8>, ptr %src 12 %v_new = insertelement <16 x i8> %v, i8 %ins, i32 1 13 store <16 x i8> %v_new, ptr %dst 14 ret void 15} 16 17define void @insert_8xi16(ptr %src, ptr %dst, i16 %ins) nounwind { 18; CHECK-LABEL: insert_8xi16: 19; CHECK: # %bb.0: 20; CHECK-NEXT: vld $vr0, $a0, 0 21; CHECK-NEXT: vinsgr2vr.h $vr0, $a2, 1 22; CHECK-NEXT: vst $vr0, $a1, 0 23; CHECK-NEXT: ret 24 %v = load volatile <8 x i16>, ptr %src 25 %v_new = insertelement <8 x i16> %v, i16 %ins, i32 1 26 store <8 x i16> %v_new, ptr %dst 27 ret void 28} 29 30define void @insert_4xi32(ptr %src, ptr %dst, i32 %ins) nounwind { 31; CHECK-LABEL: insert_4xi32: 32; CHECK: # %bb.0: 33; CHECK-NEXT: vld $vr0, $a0, 0 34; CHECK-NEXT: vinsgr2vr.w $vr0, $a2, 1 35; CHECK-NEXT: vst $vr0, $a1, 0 36; CHECK-NEXT: ret 37 %v = load volatile <4 x i32>, ptr %src 38 %v_new = insertelement <4 x i32> %v, i32 %ins, i32 1 39 store <4 x i32> %v_new, ptr %dst 40 ret void 41} 42 43define void @insert_2xi64(ptr %src, ptr %dst, i64 %ins) nounwind { 44; CHECK-LABEL: insert_2xi64: 45; CHECK: # %bb.0: 46; CHECK-NEXT: vld $vr0, $a0, 0 47; CHECK-NEXT: vinsgr2vr.d $vr0, $a2, 1 48; CHECK-NEXT: vst $vr0, $a1, 0 49; CHECK-NEXT: ret 50 %v = load volatile <2 x i64>, ptr %src 51 %v_new = insertelement <2 x i64> %v, i64 %ins, i32 1 52 store <2 x i64> %v_new, ptr %dst 53 ret void 54} 55 56define void @insert_4xfloat(ptr %src, ptr %dst, float %ins) nounwind { 57; CHECK-LABEL: insert_4xfloat: 58; CHECK: # %bb.0: 59; CHECK-NEXT: vld $vr1, $a0, 0 60; CHECK-NEXT: movfr2gr.s $a0, $fa0 61; CHECK-NEXT: vinsgr2vr.w $vr1, $a0, 1 62; CHECK-NEXT: vst $vr1, $a1, 0 63; CHECK-NEXT: ret 64 %v = load volatile <4 x float>, ptr %src 65 %v_new = insertelement <4 x float> %v, float %ins, i32 1 66 store <4 x float> %v_new, ptr %dst 67 ret void 68} 69 70define void @insert_2xdouble(ptr %src, ptr %dst, double %ins) nounwind { 71; CHECK-LABEL: insert_2xdouble: 72; CHECK: # %bb.0: 73; CHECK-NEXT: vld $vr1, $a0, 0 74; CHECK-NEXT: movfr2gr.d $a0, $fa0 75; CHECK-NEXT: vinsgr2vr.d $vr1, $a0, 1 76; CHECK-NEXT: vst $vr1, $a1, 0 77; CHECK-NEXT: ret 78 %v = load volatile <2 x double>, ptr %src 79 %v_new = insertelement <2 x double> %v, double %ins, i32 1 80 store <2 x double> %v_new, ptr %dst 81 ret void 82} 83 84define void @insert_16xi8_idx(ptr %src, ptr %dst, i8 %ins, i32 %idx) nounwind { 85; CHECK-LABEL: insert_16xi8_idx: 86; CHECK: # %bb.0: 87; CHECK-NEXT: addi.d $sp, $sp, -16 88; CHECK-NEXT: vld $vr0, $a0, 0 89; CHECK-NEXT: vst $vr0, $sp, 0 90; CHECK-NEXT: addi.d $a0, $sp, 0 91; CHECK-NEXT: bstrins.d $a0, $a3, 3, 0 92; CHECK-NEXT: st.b $a2, $a0, 0 93; CHECK-NEXT: vld $vr0, $sp, 0 94; CHECK-NEXT: vst $vr0, $a1, 0 95; CHECK-NEXT: addi.d $sp, $sp, 16 96; CHECK-NEXT: ret 97 %v = load volatile <16 x i8>, ptr %src 98 %v_new = insertelement <16 x i8> %v, i8 %ins, i32 %idx 99 store <16 x i8> %v_new, ptr %dst 100 ret void 101} 102 103define void @insert_8xi16_idx(ptr %src, ptr %dst, i16 %ins, i32 %idx) nounwind { 104; CHECK-LABEL: insert_8xi16_idx: 105; CHECK: # %bb.0: 106; CHECK-NEXT: addi.d $sp, $sp, -16 107; CHECK-NEXT: vld $vr0, $a0, 0 108; CHECK-NEXT: vst $vr0, $sp, 0 109; CHECK-NEXT: addi.d $a0, $sp, 0 110; CHECK-NEXT: bstrins.d $a0, $a3, 3, 1 111; CHECK-NEXT: st.h $a2, $a0, 0 112; CHECK-NEXT: vld $vr0, $sp, 0 113; CHECK-NEXT: vst $vr0, $a1, 0 114; CHECK-NEXT: addi.d $sp, $sp, 16 115; CHECK-NEXT: ret 116 %v = load volatile <8 x i16>, ptr %src 117 %v_new = insertelement <8 x i16> %v, i16 %ins, i32 %idx 118 store <8 x i16> %v_new, ptr %dst 119 ret void 120} 121 122define void @insert_4xi32_idx(ptr %src, ptr %dst, i32 %ins, i32 %idx) nounwind { 123; CHECK-LABEL: insert_4xi32_idx: 124; CHECK: # %bb.0: 125; CHECK-NEXT: addi.d $sp, $sp, -16 126; CHECK-NEXT: vld $vr0, $a0, 0 127; CHECK-NEXT: vst $vr0, $sp, 0 128; CHECK-NEXT: addi.d $a0, $sp, 0 129; CHECK-NEXT: bstrins.d $a0, $a3, 3, 2 130; CHECK-NEXT: st.w $a2, $a0, 0 131; CHECK-NEXT: vld $vr0, $sp, 0 132; CHECK-NEXT: vst $vr0, $a1, 0 133; CHECK-NEXT: addi.d $sp, $sp, 16 134; CHECK-NEXT: ret 135 %v = load volatile <4 x i32>, ptr %src 136 %v_new = insertelement <4 x i32> %v, i32 %ins, i32 %idx 137 store <4 x i32> %v_new, ptr %dst 138 ret void 139} 140 141define void @insert_2xi64_idx(ptr %src, ptr %dst, i64 %ins, i32 %idx) nounwind { 142; CHECK-LABEL: insert_2xi64_idx: 143; CHECK: # %bb.0: 144; CHECK-NEXT: addi.d $sp, $sp, -16 145; CHECK-NEXT: vld $vr0, $a0, 0 146; CHECK-NEXT: vst $vr0, $sp, 0 147; CHECK-NEXT: addi.d $a0, $sp, 0 148; CHECK-NEXT: bstrins.d $a0, $a3, 3, 3 149; CHECK-NEXT: st.d $a2, $a0, 0 150; CHECK-NEXT: vld $vr0, $sp, 0 151; CHECK-NEXT: vst $vr0, $a1, 0 152; CHECK-NEXT: addi.d $sp, $sp, 16 153; CHECK-NEXT: ret 154 %v = load volatile <2 x i64>, ptr %src 155 %v_new = insertelement <2 x i64> %v, i64 %ins, i32 %idx 156 store <2 x i64> %v_new, ptr %dst 157 ret void 158} 159 160define void @insert_4xfloat_idx(ptr %src, ptr %dst, float %ins, i32 %idx) nounwind { 161; CHECK-LABEL: insert_4xfloat_idx: 162; CHECK: # %bb.0: 163; CHECK-NEXT: addi.d $sp, $sp, -16 164; CHECK-NEXT: vld $vr1, $a0, 0 165; CHECK-NEXT: vst $vr1, $sp, 0 166; CHECK-NEXT: addi.d $a0, $sp, 0 167; CHECK-NEXT: bstrins.d $a0, $a2, 3, 2 168; CHECK-NEXT: fst.s $fa0, $a0, 0 169; CHECK-NEXT: vld $vr0, $sp, 0 170; CHECK-NEXT: vst $vr0, $a1, 0 171; CHECK-NEXT: addi.d $sp, $sp, 16 172; CHECK-NEXT: ret 173 %v = load volatile <4 x float>, ptr %src 174 %v_new = insertelement <4 x float> %v, float %ins, i32 %idx 175 store <4 x float> %v_new, ptr %dst 176 ret void 177} 178 179define void @insert_2xdouble_idx(ptr %src, ptr %dst, double %ins, i32 %idx) nounwind { 180; CHECK-LABEL: insert_2xdouble_idx: 181; CHECK: # %bb.0: 182; CHECK-NEXT: addi.d $sp, $sp, -16 183; CHECK-NEXT: vld $vr1, $a0, 0 184; CHECK-NEXT: vst $vr1, $sp, 0 185; CHECK-NEXT: addi.d $a0, $sp, 0 186; CHECK-NEXT: bstrins.d $a0, $a2, 3, 3 187; CHECK-NEXT: fst.d $fa0, $a0, 0 188; CHECK-NEXT: vld $vr0, $sp, 0 189; CHECK-NEXT: vst $vr0, $a1, 0 190; CHECK-NEXT: addi.d $sp, $sp, 16 191; CHECK-NEXT: ret 192 %v = load volatile <2 x double>, ptr %src 193 %v_new = insertelement <2 x double> %v, double %ins, i32 %idx 194 store <2 x double> %v_new, ptr %dst 195 ret void 196} 197