1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 2; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s 3 4define void @fmul_v4f32(ptr %res, ptr %a0, ptr %a1) nounwind { 5; CHECK-LABEL: fmul_v4f32: 6; CHECK: # %bb.0: # %entry 7; CHECK-NEXT: vld $vr0, $a1, 0 8; CHECK-NEXT: vld $vr1, $a2, 0 9; CHECK-NEXT: vfmul.s $vr0, $vr0, $vr1 10; CHECK-NEXT: vst $vr0, $a0, 0 11; CHECK-NEXT: ret 12entry: 13 %v0 = load <4 x float>, ptr %a0 14 %v1 = load <4 x float>, ptr %a1 15 %v2 = fmul <4 x float> %v0, %v1 16 store <4 x float> %v2, ptr %res 17 ret void 18} 19 20define void @fmul_v2f64(ptr %res, ptr %a0, ptr %a1) nounwind { 21; CHECK-LABEL: fmul_v2f64: 22; CHECK: # %bb.0: # %entry 23; CHECK-NEXT: vld $vr0, $a1, 0 24; CHECK-NEXT: vld $vr1, $a2, 0 25; CHECK-NEXT: vfmul.d $vr0, $vr0, $vr1 26; CHECK-NEXT: vst $vr0, $a0, 0 27; CHECK-NEXT: ret 28entry: 29 %v0 = load <2 x double>, ptr %a0 30 %v1 = load <2 x double>, ptr %a1 31 %v2 = fmul <2 x double> %v0, %v1 32 store <2 x double> %v2, ptr %res 33 ret void 34} 35