xref: /llvm-project/llvm/test/CodeGen/LoongArch/lsx/intrinsic-subw.ll (revision f3aa4416319aed198841401c6c9dc2e49afe2507) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
3
4declare <8 x i16> @llvm.loongarch.lsx.vsubwev.h.b(<16 x i8>, <16 x i8>)
5
6define <8 x i16> @lsx_vsubwev_h_b(<16 x i8> %va, <16 x i8> %vb) nounwind {
7; CHECK-LABEL: lsx_vsubwev_h_b:
8; CHECK:       # %bb.0: # %entry
9; CHECK-NEXT:    vsubwev.h.b $vr0, $vr0, $vr1
10; CHECK-NEXT:    ret
11entry:
12  %res = call <8 x i16> @llvm.loongarch.lsx.vsubwev.h.b(<16 x i8> %va, <16 x i8> %vb)
13  ret <8 x i16> %res
14}
15
16declare <4 x i32> @llvm.loongarch.lsx.vsubwev.w.h(<8 x i16>, <8 x i16>)
17
18define <4 x i32> @lsx_vsubwev_w_h(<8 x i16> %va, <8 x i16> %vb) nounwind {
19; CHECK-LABEL: lsx_vsubwev_w_h:
20; CHECK:       # %bb.0: # %entry
21; CHECK-NEXT:    vsubwev.w.h $vr0, $vr0, $vr1
22; CHECK-NEXT:    ret
23entry:
24  %res = call <4 x i32> @llvm.loongarch.lsx.vsubwev.w.h(<8 x i16> %va, <8 x i16> %vb)
25  ret <4 x i32> %res
26}
27
28declare <2 x i64> @llvm.loongarch.lsx.vsubwev.d.w(<4 x i32>, <4 x i32>)
29
30define <2 x i64> @lsx_vsubwev_d_w(<4 x i32> %va, <4 x i32> %vb) nounwind {
31; CHECK-LABEL: lsx_vsubwev_d_w:
32; CHECK:       # %bb.0: # %entry
33; CHECK-NEXT:    vsubwev.d.w $vr0, $vr0, $vr1
34; CHECK-NEXT:    ret
35entry:
36  %res = call <2 x i64> @llvm.loongarch.lsx.vsubwev.d.w(<4 x i32> %va, <4 x i32> %vb)
37  ret <2 x i64> %res
38}
39
40declare <2 x i64> @llvm.loongarch.lsx.vsubwev.q.d(<2 x i64>, <2 x i64>)
41
42define <2 x i64> @lsx_vsubwev_q_d(<2 x i64> %va, <2 x i64> %vb) nounwind {
43; CHECK-LABEL: lsx_vsubwev_q_d:
44; CHECK:       # %bb.0: # %entry
45; CHECK-NEXT:    vsubwev.q.d $vr0, $vr0, $vr1
46; CHECK-NEXT:    ret
47entry:
48  %res = call <2 x i64> @llvm.loongarch.lsx.vsubwev.q.d(<2 x i64> %va, <2 x i64> %vb)
49  ret <2 x i64> %res
50}
51
52declare <8 x i16> @llvm.loongarch.lsx.vsubwev.h.bu(<16 x i8>, <16 x i8>)
53
54define <8 x i16> @lsx_vsubwev_h_bu(<16 x i8> %va, <16 x i8> %vb) nounwind {
55; CHECK-LABEL: lsx_vsubwev_h_bu:
56; CHECK:       # %bb.0: # %entry
57; CHECK-NEXT:    vsubwev.h.bu $vr0, $vr0, $vr1
58; CHECK-NEXT:    ret
59entry:
60  %res = call <8 x i16> @llvm.loongarch.lsx.vsubwev.h.bu(<16 x i8> %va, <16 x i8> %vb)
61  ret <8 x i16> %res
62}
63
64declare <4 x i32> @llvm.loongarch.lsx.vsubwev.w.hu(<8 x i16>, <8 x i16>)
65
66define <4 x i32> @lsx_vsubwev_w_hu(<8 x i16> %va, <8 x i16> %vb) nounwind {
67; CHECK-LABEL: lsx_vsubwev_w_hu:
68; CHECK:       # %bb.0: # %entry
69; CHECK-NEXT:    vsubwev.w.hu $vr0, $vr0, $vr1
70; CHECK-NEXT:    ret
71entry:
72  %res = call <4 x i32> @llvm.loongarch.lsx.vsubwev.w.hu(<8 x i16> %va, <8 x i16> %vb)
73  ret <4 x i32> %res
74}
75
76declare <2 x i64> @llvm.loongarch.lsx.vsubwev.d.wu(<4 x i32>, <4 x i32>)
77
78define <2 x i64> @lsx_vsubwev_d_wu(<4 x i32> %va, <4 x i32> %vb) nounwind {
79; CHECK-LABEL: lsx_vsubwev_d_wu:
80; CHECK:       # %bb.0: # %entry
81; CHECK-NEXT:    vsubwev.d.wu $vr0, $vr0, $vr1
82; CHECK-NEXT:    ret
83entry:
84  %res = call <2 x i64> @llvm.loongarch.lsx.vsubwev.d.wu(<4 x i32> %va, <4 x i32> %vb)
85  ret <2 x i64> %res
86}
87
88declare <2 x i64> @llvm.loongarch.lsx.vsubwev.q.du(<2 x i64>, <2 x i64>)
89
90define <2 x i64> @lsx_vsubwev_q_du(<2 x i64> %va, <2 x i64> %vb) nounwind {
91; CHECK-LABEL: lsx_vsubwev_q_du:
92; CHECK:       # %bb.0: # %entry
93; CHECK-NEXT:    vsubwev.q.du $vr0, $vr0, $vr1
94; CHECK-NEXT:    ret
95entry:
96  %res = call <2 x i64> @llvm.loongarch.lsx.vsubwev.q.du(<2 x i64> %va, <2 x i64> %vb)
97  ret <2 x i64> %res
98}
99
100declare <8 x i16> @llvm.loongarch.lsx.vsubwod.h.b(<16 x i8>, <16 x i8>)
101
102define <8 x i16> @lsx_vsubwod_h_b(<16 x i8> %va, <16 x i8> %vb) nounwind {
103; CHECK-LABEL: lsx_vsubwod_h_b:
104; CHECK:       # %bb.0: # %entry
105; CHECK-NEXT:    vsubwod.h.b $vr0, $vr0, $vr1
106; CHECK-NEXT:    ret
107entry:
108  %res = call <8 x i16> @llvm.loongarch.lsx.vsubwod.h.b(<16 x i8> %va, <16 x i8> %vb)
109  ret <8 x i16> %res
110}
111
112declare <4 x i32> @llvm.loongarch.lsx.vsubwod.w.h(<8 x i16>, <8 x i16>)
113
114define <4 x i32> @lsx_vsubwod_w_h(<8 x i16> %va, <8 x i16> %vb) nounwind {
115; CHECK-LABEL: lsx_vsubwod_w_h:
116; CHECK:       # %bb.0: # %entry
117; CHECK-NEXT:    vsubwod.w.h $vr0, $vr0, $vr1
118; CHECK-NEXT:    ret
119entry:
120  %res = call <4 x i32> @llvm.loongarch.lsx.vsubwod.w.h(<8 x i16> %va, <8 x i16> %vb)
121  ret <4 x i32> %res
122}
123
124declare <2 x i64> @llvm.loongarch.lsx.vsubwod.d.w(<4 x i32>, <4 x i32>)
125
126define <2 x i64> @lsx_vsubwod_d_w(<4 x i32> %va, <4 x i32> %vb) nounwind {
127; CHECK-LABEL: lsx_vsubwod_d_w:
128; CHECK:       # %bb.0: # %entry
129; CHECK-NEXT:    vsubwod.d.w $vr0, $vr0, $vr1
130; CHECK-NEXT:    ret
131entry:
132  %res = call <2 x i64> @llvm.loongarch.lsx.vsubwod.d.w(<4 x i32> %va, <4 x i32> %vb)
133  ret <2 x i64> %res
134}
135
136declare <2 x i64> @llvm.loongarch.lsx.vsubwod.q.d(<2 x i64>, <2 x i64>)
137
138define <2 x i64> @lsx_vsubwod_q_d(<2 x i64> %va, <2 x i64> %vb) nounwind {
139; CHECK-LABEL: lsx_vsubwod_q_d:
140; CHECK:       # %bb.0: # %entry
141; CHECK-NEXT:    vsubwod.q.d $vr0, $vr0, $vr1
142; CHECK-NEXT:    ret
143entry:
144  %res = call <2 x i64> @llvm.loongarch.lsx.vsubwod.q.d(<2 x i64> %va, <2 x i64> %vb)
145  ret <2 x i64> %res
146}
147
148declare <8 x i16> @llvm.loongarch.lsx.vsubwod.h.bu(<16 x i8>, <16 x i8>)
149
150define <8 x i16> @lsx_vsubwod_h_bu(<16 x i8> %va, <16 x i8> %vb) nounwind {
151; CHECK-LABEL: lsx_vsubwod_h_bu:
152; CHECK:       # %bb.0: # %entry
153; CHECK-NEXT:    vsubwod.h.bu $vr0, $vr0, $vr1
154; CHECK-NEXT:    ret
155entry:
156  %res = call <8 x i16> @llvm.loongarch.lsx.vsubwod.h.bu(<16 x i8> %va, <16 x i8> %vb)
157  ret <8 x i16> %res
158}
159
160declare <4 x i32> @llvm.loongarch.lsx.vsubwod.w.hu(<8 x i16>, <8 x i16>)
161
162define <4 x i32> @lsx_vsubwod_w_hu(<8 x i16> %va, <8 x i16> %vb) nounwind {
163; CHECK-LABEL: lsx_vsubwod_w_hu:
164; CHECK:       # %bb.0: # %entry
165; CHECK-NEXT:    vsubwod.w.hu $vr0, $vr0, $vr1
166; CHECK-NEXT:    ret
167entry:
168  %res = call <4 x i32> @llvm.loongarch.lsx.vsubwod.w.hu(<8 x i16> %va, <8 x i16> %vb)
169  ret <4 x i32> %res
170}
171
172declare <2 x i64> @llvm.loongarch.lsx.vsubwod.d.wu(<4 x i32>, <4 x i32>)
173
174define <2 x i64> @lsx_vsubwod_d_wu(<4 x i32> %va, <4 x i32> %vb) nounwind {
175; CHECK-LABEL: lsx_vsubwod_d_wu:
176; CHECK:       # %bb.0: # %entry
177; CHECK-NEXT:    vsubwod.d.wu $vr0, $vr0, $vr1
178; CHECK-NEXT:    ret
179entry:
180  %res = call <2 x i64> @llvm.loongarch.lsx.vsubwod.d.wu(<4 x i32> %va, <4 x i32> %vb)
181  ret <2 x i64> %res
182}
183
184declare <2 x i64> @llvm.loongarch.lsx.vsubwod.q.du(<2 x i64>, <2 x i64>)
185
186define <2 x i64> @lsx_vsubwod_q_du(<2 x i64> %va, <2 x i64> %vb) nounwind {
187; CHECK-LABEL: lsx_vsubwod_q_du:
188; CHECK:       # %bb.0: # %entry
189; CHECK-NEXT:    vsubwod.q.du $vr0, $vr0, $vr1
190; CHECK-NEXT:    ret
191entry:
192  %res = call <2 x i64> @llvm.loongarch.lsx.vsubwod.q.du(<2 x i64> %va, <2 x i64> %vb)
193  ret <2 x i64> %res
194}
195