xref: /llvm-project/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssran.ll (revision f3aa4416319aed198841401c6c9dc2e49afe2507) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
3
4declare <16 x i8> @llvm.loongarch.lsx.vssran.b.h(<8 x i16>, <8 x i16>)
5
6define <16 x i8> @lsx_vssran_b_h(<8 x i16> %va, <8 x i16> %vb) nounwind {
7; CHECK-LABEL: lsx_vssran_b_h:
8; CHECK:       # %bb.0: # %entry
9; CHECK-NEXT:    vssran.b.h $vr0, $vr0, $vr1
10; CHECK-NEXT:    ret
11entry:
12  %res = call <16 x i8> @llvm.loongarch.lsx.vssran.b.h(<8 x i16> %va, <8 x i16> %vb)
13  ret <16 x i8> %res
14}
15
16declare <8 x i16> @llvm.loongarch.lsx.vssran.h.w(<4 x i32>, <4 x i32>)
17
18define <8 x i16> @lsx_vssran_h_w(<4 x i32> %va, <4 x i32> %vb) nounwind {
19; CHECK-LABEL: lsx_vssran_h_w:
20; CHECK:       # %bb.0: # %entry
21; CHECK-NEXT:    vssran.h.w $vr0, $vr0, $vr1
22; CHECK-NEXT:    ret
23entry:
24  %res = call <8 x i16> @llvm.loongarch.lsx.vssran.h.w(<4 x i32> %va, <4 x i32> %vb)
25  ret <8 x i16> %res
26}
27
28declare <4 x i32> @llvm.loongarch.lsx.vssran.w.d(<2 x i64>, <2 x i64>)
29
30define <4 x i32> @lsx_vssran_w_d(<2 x i64> %va, <2 x i64> %vb) nounwind {
31; CHECK-LABEL: lsx_vssran_w_d:
32; CHECK:       # %bb.0: # %entry
33; CHECK-NEXT:    vssran.w.d $vr0, $vr0, $vr1
34; CHECK-NEXT:    ret
35entry:
36  %res = call <4 x i32> @llvm.loongarch.lsx.vssran.w.d(<2 x i64> %va, <2 x i64> %vb)
37  ret <4 x i32> %res
38}
39
40declare <16 x i8> @llvm.loongarch.lsx.vssran.bu.h(<8 x i16>, <8 x i16>)
41
42define <16 x i8> @lsx_vssran_bu_h(<8 x i16> %va, <8 x i16> %vb) nounwind {
43; CHECK-LABEL: lsx_vssran_bu_h:
44; CHECK:       # %bb.0: # %entry
45; CHECK-NEXT:    vssran.bu.h $vr0, $vr0, $vr1
46; CHECK-NEXT:    ret
47entry:
48  %res = call <16 x i8> @llvm.loongarch.lsx.vssran.bu.h(<8 x i16> %va, <8 x i16> %vb)
49  ret <16 x i8> %res
50}
51
52declare <8 x i16> @llvm.loongarch.lsx.vssran.hu.w(<4 x i32>, <4 x i32>)
53
54define <8 x i16> @lsx_vssran_hu_w(<4 x i32> %va, <4 x i32> %vb) nounwind {
55; CHECK-LABEL: lsx_vssran_hu_w:
56; CHECK:       # %bb.0: # %entry
57; CHECK-NEXT:    vssran.hu.w $vr0, $vr0, $vr1
58; CHECK-NEXT:    ret
59entry:
60  %res = call <8 x i16> @llvm.loongarch.lsx.vssran.hu.w(<4 x i32> %va, <4 x i32> %vb)
61  ret <8 x i16> %res
62}
63
64declare <4 x i32> @llvm.loongarch.lsx.vssran.wu.d(<2 x i64>, <2 x i64>)
65
66define <4 x i32> @lsx_vssran_wu_d(<2 x i64> %va, <2 x i64> %vb) nounwind {
67; CHECK-LABEL: lsx_vssran_wu_d:
68; CHECK:       # %bb.0: # %entry
69; CHECK-NEXT:    vssran.wu.d $vr0, $vr0, $vr1
70; CHECK-NEXT:    ret
71entry:
72  %res = call <4 x i32> @llvm.loongarch.lsx.vssran.wu.d(<2 x i64> %va, <2 x i64> %vb)
73  ret <4 x i32> %res
74}
75