1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s 3 4declare <16 x i8> @llvm.loongarch.lsx.vmod.b(<16 x i8>, <16 x i8>) 5 6define <16 x i8> @lsx_vmod_b(<16 x i8> %va, <16 x i8> %vb) nounwind { 7; CHECK-LABEL: lsx_vmod_b: 8; CHECK: # %bb.0: # %entry 9; CHECK-NEXT: vmod.b $vr0, $vr0, $vr1 10; CHECK-NEXT: ret 11entry: 12 %res = call <16 x i8> @llvm.loongarch.lsx.vmod.b(<16 x i8> %va, <16 x i8> %vb) 13 ret <16 x i8> %res 14} 15 16declare <8 x i16> @llvm.loongarch.lsx.vmod.h(<8 x i16>, <8 x i16>) 17 18define <8 x i16> @lsx_vmod_h(<8 x i16> %va, <8 x i16> %vb) nounwind { 19; CHECK-LABEL: lsx_vmod_h: 20; CHECK: # %bb.0: # %entry 21; CHECK-NEXT: vmod.h $vr0, $vr0, $vr1 22; CHECK-NEXT: ret 23entry: 24 %res = call <8 x i16> @llvm.loongarch.lsx.vmod.h(<8 x i16> %va, <8 x i16> %vb) 25 ret <8 x i16> %res 26} 27 28declare <4 x i32> @llvm.loongarch.lsx.vmod.w(<4 x i32>, <4 x i32>) 29 30define <4 x i32> @lsx_vmod_w(<4 x i32> %va, <4 x i32> %vb) nounwind { 31; CHECK-LABEL: lsx_vmod_w: 32; CHECK: # %bb.0: # %entry 33; CHECK-NEXT: vmod.w $vr0, $vr0, $vr1 34; CHECK-NEXT: ret 35entry: 36 %res = call <4 x i32> @llvm.loongarch.lsx.vmod.w(<4 x i32> %va, <4 x i32> %vb) 37 ret <4 x i32> %res 38} 39 40declare <2 x i64> @llvm.loongarch.lsx.vmod.d(<2 x i64>, <2 x i64>) 41 42define <2 x i64> @lsx_vmod_d(<2 x i64> %va, <2 x i64> %vb) nounwind { 43; CHECK-LABEL: lsx_vmod_d: 44; CHECK: # %bb.0: # %entry 45; CHECK-NEXT: vmod.d $vr0, $vr0, $vr1 46; CHECK-NEXT: ret 47entry: 48 %res = call <2 x i64> @llvm.loongarch.lsx.vmod.d(<2 x i64> %va, <2 x i64> %vb) 49 ret <2 x i64> %res 50} 51 52declare <16 x i8> @llvm.loongarch.lsx.vmod.bu(<16 x i8>, <16 x i8>) 53 54define <16 x i8> @lsx_vmod_bu(<16 x i8> %va, <16 x i8> %vb) nounwind { 55; CHECK-LABEL: lsx_vmod_bu: 56; CHECK: # %bb.0: # %entry 57; CHECK-NEXT: vmod.bu $vr0, $vr0, $vr1 58; CHECK-NEXT: ret 59entry: 60 %res = call <16 x i8> @llvm.loongarch.lsx.vmod.bu(<16 x i8> %va, <16 x i8> %vb) 61 ret <16 x i8> %res 62} 63 64declare <8 x i16> @llvm.loongarch.lsx.vmod.hu(<8 x i16>, <8 x i16>) 65 66define <8 x i16> @lsx_vmod_hu(<8 x i16> %va, <8 x i16> %vb) nounwind { 67; CHECK-LABEL: lsx_vmod_hu: 68; CHECK: # %bb.0: # %entry 69; CHECK-NEXT: vmod.hu $vr0, $vr0, $vr1 70; CHECK-NEXT: ret 71entry: 72 %res = call <8 x i16> @llvm.loongarch.lsx.vmod.hu(<8 x i16> %va, <8 x i16> %vb) 73 ret <8 x i16> %res 74} 75 76declare <4 x i32> @llvm.loongarch.lsx.vmod.wu(<4 x i32>, <4 x i32>) 77 78define <4 x i32> @lsx_vmod_wu(<4 x i32> %va, <4 x i32> %vb) nounwind { 79; CHECK-LABEL: lsx_vmod_wu: 80; CHECK: # %bb.0: # %entry 81; CHECK-NEXT: vmod.wu $vr0, $vr0, $vr1 82; CHECK-NEXT: ret 83entry: 84 %res = call <4 x i32> @llvm.loongarch.lsx.vmod.wu(<4 x i32> %va, <4 x i32> %vb) 85 ret <4 x i32> %res 86} 87 88declare <2 x i64> @llvm.loongarch.lsx.vmod.du(<2 x i64>, <2 x i64>) 89 90define <2 x i64> @lsx_vmod_du(<2 x i64> %va, <2 x i64> %vb) nounwind { 91; CHECK-LABEL: lsx_vmod_du: 92; CHECK: # %bb.0: # %entry 93; CHECK-NEXT: vmod.du $vr0, $vr0, $vr1 94; CHECK-NEXT: ret 95entry: 96 %res = call <2 x i64> @llvm.loongarch.lsx.vmod.du(<2 x i64> %va, <2 x i64> %vb) 97 ret <2 x i64> %res 98} 99