1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s 3 4declare <16 x i8> @llvm.loongarch.lsx.vmax.b(<16 x i8>, <16 x i8>) 5 6define <16 x i8> @lsx_vmax_b(<16 x i8> %va, <16 x i8> %vb) nounwind { 7; CHECK-LABEL: lsx_vmax_b: 8; CHECK: # %bb.0: # %entry 9; CHECK-NEXT: vmax.b $vr0, $vr0, $vr1 10; CHECK-NEXT: ret 11entry: 12 %res = call <16 x i8> @llvm.loongarch.lsx.vmax.b(<16 x i8> %va, <16 x i8> %vb) 13 ret <16 x i8> %res 14} 15 16declare <8 x i16> @llvm.loongarch.lsx.vmax.h(<8 x i16>, <8 x i16>) 17 18define <8 x i16> @lsx_vmax_h(<8 x i16> %va, <8 x i16> %vb) nounwind { 19; CHECK-LABEL: lsx_vmax_h: 20; CHECK: # %bb.0: # %entry 21; CHECK-NEXT: vmax.h $vr0, $vr0, $vr1 22; CHECK-NEXT: ret 23entry: 24 %res = call <8 x i16> @llvm.loongarch.lsx.vmax.h(<8 x i16> %va, <8 x i16> %vb) 25 ret <8 x i16> %res 26} 27 28declare <4 x i32> @llvm.loongarch.lsx.vmax.w(<4 x i32>, <4 x i32>) 29 30define <4 x i32> @lsx_vmax_w(<4 x i32> %va, <4 x i32> %vb) nounwind { 31; CHECK-LABEL: lsx_vmax_w: 32; CHECK: # %bb.0: # %entry 33; CHECK-NEXT: vmax.w $vr0, $vr0, $vr1 34; CHECK-NEXT: ret 35entry: 36 %res = call <4 x i32> @llvm.loongarch.lsx.vmax.w(<4 x i32> %va, <4 x i32> %vb) 37 ret <4 x i32> %res 38} 39 40declare <2 x i64> @llvm.loongarch.lsx.vmax.d(<2 x i64>, <2 x i64>) 41 42define <2 x i64> @lsx_vmax_d(<2 x i64> %va, <2 x i64> %vb) nounwind { 43; CHECK-LABEL: lsx_vmax_d: 44; CHECK: # %bb.0: # %entry 45; CHECK-NEXT: vmax.d $vr0, $vr0, $vr1 46; CHECK-NEXT: ret 47entry: 48 %res = call <2 x i64> @llvm.loongarch.lsx.vmax.d(<2 x i64> %va, <2 x i64> %vb) 49 ret <2 x i64> %res 50} 51 52declare <16 x i8> @llvm.loongarch.lsx.vmaxi.b(<16 x i8>, i32) 53 54define <16 x i8> @lsx_vmaxi_b(<16 x i8> %va) nounwind { 55; CHECK-LABEL: lsx_vmaxi_b: 56; CHECK: # %bb.0: # %entry 57; CHECK-NEXT: vmaxi.b $vr0, $vr0, -16 58; CHECK-NEXT: ret 59entry: 60 %res = call <16 x i8> @llvm.loongarch.lsx.vmaxi.b(<16 x i8> %va, i32 -16) 61 ret <16 x i8> %res 62} 63 64declare <8 x i16> @llvm.loongarch.lsx.vmaxi.h(<8 x i16>, i32) 65 66define <8 x i16> @lsx_vmaxi_h(<8 x i16> %va) nounwind { 67; CHECK-LABEL: lsx_vmaxi_h: 68; CHECK: # %bb.0: # %entry 69; CHECK-NEXT: vmaxi.h $vr0, $vr0, -16 70; CHECK-NEXT: ret 71entry: 72 %res = call <8 x i16> @llvm.loongarch.lsx.vmaxi.h(<8 x i16> %va, i32 -16) 73 ret <8 x i16> %res 74} 75 76declare <4 x i32> @llvm.loongarch.lsx.vmaxi.w(<4 x i32>, i32) 77 78define <4 x i32> @lsx_vmaxi_w(<4 x i32> %va) nounwind { 79; CHECK-LABEL: lsx_vmaxi_w: 80; CHECK: # %bb.0: # %entry 81; CHECK-NEXT: vmaxi.w $vr0, $vr0, 15 82; CHECK-NEXT: ret 83entry: 84 %res = call <4 x i32> @llvm.loongarch.lsx.vmaxi.w(<4 x i32> %va, i32 15) 85 ret <4 x i32> %res 86} 87 88declare <2 x i64> @llvm.loongarch.lsx.vmaxi.d(<2 x i64>, i32) 89 90define <2 x i64> @lsx_vmaxi_d(<2 x i64> %va) nounwind { 91; CHECK-LABEL: lsx_vmaxi_d: 92; CHECK: # %bb.0: # %entry 93; CHECK-NEXT: vmaxi.d $vr0, $vr0, 15 94; CHECK-NEXT: ret 95entry: 96 %res = call <2 x i64> @llvm.loongarch.lsx.vmaxi.d(<2 x i64> %va, i32 15) 97 ret <2 x i64> %res 98} 99 100declare <16 x i8> @llvm.loongarch.lsx.vmax.bu(<16 x i8>, <16 x i8>) 101 102define <16 x i8> @lsx_vmax_bu(<16 x i8> %va, <16 x i8> %vb) nounwind { 103; CHECK-LABEL: lsx_vmax_bu: 104; CHECK: # %bb.0: # %entry 105; CHECK-NEXT: vmax.bu $vr0, $vr0, $vr1 106; CHECK-NEXT: ret 107entry: 108 %res = call <16 x i8> @llvm.loongarch.lsx.vmax.bu(<16 x i8> %va, <16 x i8> %vb) 109 ret <16 x i8> %res 110} 111 112declare <8 x i16> @llvm.loongarch.lsx.vmax.hu(<8 x i16>, <8 x i16>) 113 114define <8 x i16> @lsx_vmax_hu(<8 x i16> %va, <8 x i16> %vb) nounwind { 115; CHECK-LABEL: lsx_vmax_hu: 116; CHECK: # %bb.0: # %entry 117; CHECK-NEXT: vmax.hu $vr0, $vr0, $vr1 118; CHECK-NEXT: ret 119entry: 120 %res = call <8 x i16> @llvm.loongarch.lsx.vmax.hu(<8 x i16> %va, <8 x i16> %vb) 121 ret <8 x i16> %res 122} 123 124declare <4 x i32> @llvm.loongarch.lsx.vmax.wu(<4 x i32>, <4 x i32>) 125 126define <4 x i32> @lsx_vmax_wu(<4 x i32> %va, <4 x i32> %vb) nounwind { 127; CHECK-LABEL: lsx_vmax_wu: 128; CHECK: # %bb.0: # %entry 129; CHECK-NEXT: vmax.wu $vr0, $vr0, $vr1 130; CHECK-NEXT: ret 131entry: 132 %res = call <4 x i32> @llvm.loongarch.lsx.vmax.wu(<4 x i32> %va, <4 x i32> %vb) 133 ret <4 x i32> %res 134} 135 136declare <2 x i64> @llvm.loongarch.lsx.vmax.du(<2 x i64>, <2 x i64>) 137 138define <2 x i64> @lsx_vmax_du(<2 x i64> %va, <2 x i64> %vb) nounwind { 139; CHECK-LABEL: lsx_vmax_du: 140; CHECK: # %bb.0: # %entry 141; CHECK-NEXT: vmax.du $vr0, $vr0, $vr1 142; CHECK-NEXT: ret 143entry: 144 %res = call <2 x i64> @llvm.loongarch.lsx.vmax.du(<2 x i64> %va, <2 x i64> %vb) 145 ret <2 x i64> %res 146} 147 148declare <16 x i8> @llvm.loongarch.lsx.vmaxi.bu(<16 x i8>, i32) 149 150define <16 x i8> @lsx_vmaxi_bu(<16 x i8> %va) nounwind { 151; CHECK-LABEL: lsx_vmaxi_bu: 152; CHECK: # %bb.0: # %entry 153; CHECK-NEXT: vmaxi.bu $vr0, $vr0, 1 154; CHECK-NEXT: ret 155entry: 156 %res = call <16 x i8> @llvm.loongarch.lsx.vmaxi.bu(<16 x i8> %va, i32 1) 157 ret <16 x i8> %res 158} 159 160declare <8 x i16> @llvm.loongarch.lsx.vmaxi.hu(<8 x i16>, i32) 161 162define <8 x i16> @lsx_vmaxi_hu(<8 x i16> %va) nounwind { 163; CHECK-LABEL: lsx_vmaxi_hu: 164; CHECK: # %bb.0: # %entry 165; CHECK-NEXT: vmaxi.hu $vr0, $vr0, 1 166; CHECK-NEXT: ret 167entry: 168 %res = call <8 x i16> @llvm.loongarch.lsx.vmaxi.hu(<8 x i16> %va, i32 1) 169 ret <8 x i16> %res 170} 171 172declare <4 x i32> @llvm.loongarch.lsx.vmaxi.wu(<4 x i32>, i32) 173 174define <4 x i32> @lsx_vmaxi_wu(<4 x i32> %va) nounwind { 175; CHECK-LABEL: lsx_vmaxi_wu: 176; CHECK: # %bb.0: # %entry 177; CHECK-NEXT: vmaxi.wu $vr0, $vr0, 31 178; CHECK-NEXT: ret 179entry: 180 %res = call <4 x i32> @llvm.loongarch.lsx.vmaxi.wu(<4 x i32> %va, i32 31) 181 ret <4 x i32> %res 182} 183 184declare <2 x i64> @llvm.loongarch.lsx.vmaxi.du(<2 x i64>, i32) 185 186define <2 x i64> @lsx_vmaxi_du(<2 x i64> %va) nounwind { 187; CHECK-LABEL: lsx_vmaxi_du: 188; CHECK: # %bb.0: # %entry 189; CHECK-NEXT: vmaxi.du $vr0, $vr0, 31 190; CHECK-NEXT: ret 191entry: 192 %res = call <2 x i64> @llvm.loongarch.lsx.vmaxi.du(<2 x i64> %va, i32 31) 193 ret <2 x i64> %res 194} 195