1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s 3 4declare <2 x i64> @llvm.loongarch.lsx.vextl.q.d(<2 x i64>) 5 6define <2 x i64> @lsx_vextl_q_d(<2 x i64> %va) nounwind { 7; CHECK-LABEL: lsx_vextl_q_d: 8; CHECK: # %bb.0: # %entry 9; CHECK-NEXT: vextl.q.d $vr0, $vr0 10; CHECK-NEXT: ret 11entry: 12 %res = call <2 x i64> @llvm.loongarch.lsx.vextl.q.d(<2 x i64> %va) 13 ret <2 x i64> %res 14} 15 16declare <2 x i64> @llvm.loongarch.lsx.vextl.qu.du(<2 x i64>) 17 18define <2 x i64> @lsx_vextl_qu_du(<2 x i64> %va) nounwind { 19; CHECK-LABEL: lsx_vextl_qu_du: 20; CHECK: # %bb.0: # %entry 21; CHECK-NEXT: vextl.qu.du $vr0, $vr0 22; CHECK-NEXT: ret 23entry: 24 %res = call <2 x i64> @llvm.loongarch.lsx.vextl.qu.du(<2 x i64> %va) 25 ret <2 x i64> %res 26} 27