1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 2; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s 3 4define void @register_vr1() nounwind { 5; CHECK-LABEL: register_vr1: 6; CHECK: # %bb.0: # %entry 7; CHECK-NEXT: #APP 8; CHECK-NEXT: vldi $vr1, 1 9; CHECK-NEXT: #NO_APP 10; CHECK-NEXT: ret 11entry: 12 %0 = tail call <2 x i64> asm sideeffect "vldi ${0:w}, 1", "={$vr1}"() 13 ret void 14} 15 16define void @register_vr7() nounwind { 17; CHECK-LABEL: register_vr7: 18; CHECK: # %bb.0: # %entry 19; CHECK-NEXT: #APP 20; CHECK-NEXT: vldi $vr7, 1 21; CHECK-NEXT: #NO_APP 22; CHECK-NEXT: ret 23entry: 24 %0 = tail call <2 x i64> asm sideeffect "vldi ${0:w}, 1", "={$vr7}"() 25 ret void 26} 27 28define void @register_vr23() nounwind { 29; CHECK-LABEL: register_vr23: 30; CHECK: # %bb.0: # %entry 31; CHECK-NEXT: #APP 32; CHECK-NEXT: vldi $vr23, 1 33; CHECK-NEXT: #NO_APP 34; CHECK-NEXT: ret 35entry: 36 %0 = tail call <2 x i64> asm sideeffect "vldi ${0:w}, 1", "={$vr23}"() 37 ret void 38} 39 40;; The lower half of the vector register '$vr31' is overlapped with 41;; the floating-point register '$f31'. And '$f31' is a callee-saved 42;; register which is preserved across calls. That's why the 43;; fst.d and fld.d instructions are emitted. 44define void @register_vr31() nounwind { 45; CHECK-LABEL: register_vr31: 46; CHECK: # %bb.0: # %entry 47; CHECK-NEXT: addi.d $sp, $sp, -16 48; CHECK-NEXT: fst.d $fs7, $sp, 8 # 8-byte Folded Spill 49; CHECK-NEXT: #APP 50; CHECK-NEXT: vldi $vr31, 1 51; CHECK-NEXT: #NO_APP 52; CHECK-NEXT: fld.d $fs7, $sp, 8 # 8-byte Folded Reload 53; CHECK-NEXT: addi.d $sp, $sp, 16 54; CHECK-NEXT: ret 55entry: 56 %0 = tail call <2 x i64> asm sideeffect "vldi ${0:w}, 1", "={$vr31}"() 57 ret void 58} 59