xref: /llvm-project/llvm/test/CodeGen/LoongArch/lsx/ctpop-ctlz.ll (revision a60a5421b60be1bce0272385fa16846ada5eed5e) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
3
4define void @ctpop_v16i8(ptr %src, ptr %dst) nounwind {
5; CHECK-LABEL: ctpop_v16i8:
6; CHECK:       # %bb.0:
7; CHECK-NEXT:    vld $vr0, $a0, 0
8; CHECK-NEXT:    vpcnt.b $vr0, $vr0
9; CHECK-NEXT:    vst $vr0, $a1, 0
10; CHECK-NEXT:    ret
11  %v = load <16 x i8>, ptr %src
12  %res = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %v)
13  store <16 x i8> %res, ptr %dst
14  ret void
15}
16
17define void @ctpop_v8i16(ptr %src, ptr %dst) nounwind {
18; CHECK-LABEL: ctpop_v8i16:
19; CHECK:       # %bb.0:
20; CHECK-NEXT:    vld $vr0, $a0, 0
21; CHECK-NEXT:    vpcnt.h $vr0, $vr0
22; CHECK-NEXT:    vst $vr0, $a1, 0
23; CHECK-NEXT:    ret
24  %v = load <8 x i16>, ptr %src
25  %res = call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %v)
26  store <8 x i16> %res, ptr %dst
27  ret void
28}
29
30define void @ctpop_v4i32(ptr %src, ptr %dst) nounwind {
31; CHECK-LABEL: ctpop_v4i32:
32; CHECK:       # %bb.0:
33; CHECK-NEXT:    vld $vr0, $a0, 0
34; CHECK-NEXT:    vpcnt.w $vr0, $vr0
35; CHECK-NEXT:    vst $vr0, $a1, 0
36; CHECK-NEXT:    ret
37  %v = load <4 x i32>, ptr %src
38  %res = call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %v)
39  store <4 x i32> %res, ptr %dst
40  ret void
41}
42
43define void @ctpop_v2i64(ptr %src, ptr %dst) nounwind {
44; CHECK-LABEL: ctpop_v2i64:
45; CHECK:       # %bb.0:
46; CHECK-NEXT:    vld $vr0, $a0, 0
47; CHECK-NEXT:    vpcnt.d $vr0, $vr0
48; CHECK-NEXT:    vst $vr0, $a1, 0
49; CHECK-NEXT:    ret
50  %v = load <2 x i64>, ptr %src
51  %res = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %v)
52  store <2 x i64> %res, ptr %dst
53  ret void
54}
55
56define void @ctlz_v16i8(ptr %src, ptr %dst) nounwind {
57; CHECK-LABEL: ctlz_v16i8:
58; CHECK:       # %bb.0:
59; CHECK-NEXT:    vld $vr0, $a0, 0
60; CHECK-NEXT:    vclz.b $vr0, $vr0
61; CHECK-NEXT:    vst $vr0, $a1, 0
62; CHECK-NEXT:    ret
63  %v = load <16 x i8>, ptr %src
64  %res = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %v, i1 false)
65  store <16 x i8> %res, ptr %dst
66  ret void
67}
68
69define void @ctlz_v8i16(ptr %src, ptr %dst) nounwind {
70; CHECK-LABEL: ctlz_v8i16:
71; CHECK:       # %bb.0:
72; CHECK-NEXT:    vld $vr0, $a0, 0
73; CHECK-NEXT:    vclz.h $vr0, $vr0
74; CHECK-NEXT:    vst $vr0, $a1, 0
75; CHECK-NEXT:    ret
76  %v = load <8 x i16>, ptr %src
77  %res = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %v, i1 false)
78  store <8 x i16> %res, ptr %dst
79  ret void
80}
81
82define void @ctlz_v4i32(ptr %src, ptr %dst) nounwind {
83; CHECK-LABEL: ctlz_v4i32:
84; CHECK:       # %bb.0:
85; CHECK-NEXT:    vld $vr0, $a0, 0
86; CHECK-NEXT:    vclz.w $vr0, $vr0
87; CHECK-NEXT:    vst $vr0, $a1, 0
88; CHECK-NEXT:    ret
89  %v = load <4 x i32>, ptr %src
90  %res = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %v, i1 false)
91  store <4 x i32> %res, ptr %dst
92  ret void
93}
94
95define void @ctlz_v2i64(ptr %src, ptr %dst) nounwind {
96; CHECK-LABEL: ctlz_v2i64:
97; CHECK:       # %bb.0:
98; CHECK-NEXT:    vld $vr0, $a0, 0
99; CHECK-NEXT:    vclz.d $vr0, $vr0
100; CHECK-NEXT:    vst $vr0, $a1, 0
101; CHECK-NEXT:    ret
102  %v = load <2 x i64>, ptr %src
103  %res = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %v, i1 false)
104  store <2 x i64> %res, ptr %dst
105  ret void
106}
107
108declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>)
109declare <8 x i16> @llvm.ctpop.v8i16(<8 x i16>)
110declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>)
111declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>)
112declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>, i1)
113declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1)
114declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1)
115declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1)
116