xref: /llvm-project/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sdiv.ll (revision a5c90e48b6f11bc6db7344503589648f76b16d80) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
3
4define void @sdiv_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind {
5; CHECK-LABEL: sdiv_v32i8:
6; CHECK:       # %bb.0: # %entry
7; CHECK-NEXT:    xvld $xr0, $a1, 0
8; CHECK-NEXT:    xvld $xr1, $a2, 0
9; CHECK-NEXT:    xvdiv.b $xr0, $xr0, $xr1
10; CHECK-NEXT:    xvst $xr0, $a0, 0
11; CHECK-NEXT:    ret
12entry:
13  %v0 = load <32 x i8>, ptr %a0
14  %v1 = load <32 x i8>, ptr %a1
15  %v2 = sdiv <32 x i8> %v0, %v1
16  store <32 x i8> %v2, ptr %res
17  ret void
18}
19
20define void @sdiv_v16i16(ptr %res, ptr %a0, ptr %a1) nounwind {
21; CHECK-LABEL: sdiv_v16i16:
22; CHECK:       # %bb.0: # %entry
23; CHECK-NEXT:    xvld $xr0, $a1, 0
24; CHECK-NEXT:    xvld $xr1, $a2, 0
25; CHECK-NEXT:    xvdiv.h $xr0, $xr0, $xr1
26; CHECK-NEXT:    xvst $xr0, $a0, 0
27; CHECK-NEXT:    ret
28entry:
29  %v0 = load <16 x i16>, ptr %a0
30  %v1 = load <16 x i16>, ptr %a1
31  %v2 = sdiv <16 x i16> %v0, %v1
32  store <16 x i16> %v2, ptr %res
33  ret void
34}
35
36define void @sdiv_v8i32(ptr %res, ptr %a0, ptr %a1) nounwind {
37; CHECK-LABEL: sdiv_v8i32:
38; CHECK:       # %bb.0: # %entry
39; CHECK-NEXT:    xvld $xr0, $a1, 0
40; CHECK-NEXT:    xvld $xr1, $a2, 0
41; CHECK-NEXT:    xvdiv.w $xr0, $xr0, $xr1
42; CHECK-NEXT:    xvst $xr0, $a0, 0
43; CHECK-NEXT:    ret
44entry:
45  %v0 = load <8 x i32>, ptr %a0
46  %v1 = load <8 x i32>, ptr %a1
47  %v2 = sdiv <8 x i32> %v0, %v1
48  store <8 x i32> %v2, ptr %res
49  ret void
50}
51
52define void @sdiv_v4i64(ptr %res, ptr %a0, ptr %a1) nounwind {
53; CHECK-LABEL: sdiv_v4i64:
54; CHECK:       # %bb.0: # %entry
55; CHECK-NEXT:    xvld $xr0, $a1, 0
56; CHECK-NEXT:    xvld $xr1, $a2, 0
57; CHECK-NEXT:    xvdiv.d $xr0, $xr0, $xr1
58; CHECK-NEXT:    xvst $xr0, $a0, 0
59; CHECK-NEXT:    ret
60entry:
61  %v0 = load <4 x i64>, ptr %a0
62  %v1 = load <4 x i64>, ptr %a1
63  %v2 = sdiv <4 x i64> %v0, %v1
64  store <4 x i64> %v2, ptr %res
65  ret void
66}
67
68define void @sdiv_v32i8_8(ptr %res, ptr %a0) nounwind {
69; CHECK-LABEL: sdiv_v32i8_8:
70; CHECK:       # %bb.0: # %entry
71; CHECK-NEXT:    xvld $xr0, $a1, 0
72; CHECK-NEXT:    xvsrai.b $xr1, $xr0, 7
73; CHECK-NEXT:    xvsrli.b $xr1, $xr1, 5
74; CHECK-NEXT:    xvadd.b $xr0, $xr0, $xr1
75; CHECK-NEXT:    xvsrai.b $xr0, $xr0, 3
76; CHECK-NEXT:    xvst $xr0, $a0, 0
77; CHECK-NEXT:    ret
78entry:
79  %v0 = load <32 x i8>, ptr %a0
80  %v1 = sdiv <32 x i8> %v0, <i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8>
81  store <32 x i8> %v1, ptr %res
82  ret void
83}
84
85define void @sdiv_v16i16_8(ptr %res, ptr %a0) nounwind {
86; CHECK-LABEL: sdiv_v16i16_8:
87; CHECK:       # %bb.0: # %entry
88; CHECK-NEXT:    xvld $xr0, $a1, 0
89; CHECK-NEXT:    xvsrai.h $xr1, $xr0, 15
90; CHECK-NEXT:    xvsrli.h $xr1, $xr1, 13
91; CHECK-NEXT:    xvadd.h $xr0, $xr0, $xr1
92; CHECK-NEXT:    xvsrai.h $xr0, $xr0, 3
93; CHECK-NEXT:    xvst $xr0, $a0, 0
94; CHECK-NEXT:    ret
95entry:
96  %v0 = load <16 x i16>, ptr %a0
97  %v1 = sdiv <16 x i16> %v0, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
98  store <16 x i16> %v1, ptr %res
99  ret void
100}
101
102define void @sdiv_v8i32_8(ptr %res, ptr %a0) nounwind {
103; CHECK-LABEL: sdiv_v8i32_8:
104; CHECK:       # %bb.0: # %entry
105; CHECK-NEXT:    xvld $xr0, $a1, 0
106; CHECK-NEXT:    xvsrai.w $xr1, $xr0, 31
107; CHECK-NEXT:    xvsrli.w $xr1, $xr1, 29
108; CHECK-NEXT:    xvadd.w $xr0, $xr0, $xr1
109; CHECK-NEXT:    xvsrai.w $xr0, $xr0, 3
110; CHECK-NEXT:    xvst $xr0, $a0, 0
111; CHECK-NEXT:    ret
112entry:
113  %v0 = load <8 x i32>, ptr %a0
114  %v1 = sdiv <8 x i32> %v0, <i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8>
115  store <8 x i32> %v1, ptr %res
116  ret void
117}
118
119define void @sdiv_v4i64_8(ptr %res, ptr %a0) nounwind {
120; CHECK-LABEL: sdiv_v4i64_8:
121; CHECK:       # %bb.0: # %entry
122; CHECK-NEXT:    xvld $xr0, $a1, 0
123; CHECK-NEXT:    xvsrai.d $xr1, $xr0, 63
124; CHECK-NEXT:    xvsrli.d $xr1, $xr1, 61
125; CHECK-NEXT:    xvadd.d $xr0, $xr0, $xr1
126; CHECK-NEXT:    xvsrai.d $xr0, $xr0, 3
127; CHECK-NEXT:    xvst $xr0, $a0, 0
128; CHECK-NEXT:    ret
129entry:
130  %v0 = load <4 x i64>, ptr %a0
131  %v1 = sdiv <4 x i64> %v0, <i64 8, i64 8, i64 8, i64 8>
132  store <4 x i64> %v1, ptr %res
133  ret void
134}
135