xref: /llvm-project/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fneg.ll (revision cdc37325669c0321328a7245083c427b229e79e9)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
3
4define void @fneg_v8f32(ptr %res, ptr %a0) nounwind {
5; CHECK-LABEL: fneg_v8f32:
6; CHECK:       # %bb.0: # %entry
7; CHECK-NEXT:    xvld $xr0, $a1, 0
8; CHECK-NEXT:    xvbitrevi.w $xr0, $xr0, 31
9; CHECK-NEXT:    xvst $xr0, $a0, 0
10; CHECK-NEXT:    ret
11entry:
12  %v0 = load <8 x float>, ptr %a0
13  %v1 = fneg <8 x float> %v0
14  store <8 x float> %v1, ptr %res
15  ret void
16}
17define void @fneg_v4f64(ptr %res, ptr %a0) nounwind {
18; CHECK-LABEL: fneg_v4f64:
19; CHECK:       # %bb.0: # %entry
20; CHECK-NEXT:    xvld $xr0, $a1, 0
21; CHECK-NEXT:    xvbitrevi.d $xr0, $xr0, 63
22; CHECK-NEXT:    xvst $xr0, $a0, 0
23; CHECK-NEXT:    ret
24entry:
25  %v0 = load <4 x double>, ptr %a0
26  %v1 = fneg <4 x double> %v0
27  store <4 x double> %v1, ptr %res
28  ret void
29}
30