1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s 3 4declare <32 x i8> @llvm.loongarch.lasx.xvsrarn.b.h(<16 x i16>, <16 x i16>) 5 6define <32 x i8> @lasx_xvsrarn_b_h(<16 x i16> %va, <16 x i16> %vb) nounwind { 7; CHECK-LABEL: lasx_xvsrarn_b_h: 8; CHECK: # %bb.0: # %entry 9; CHECK-NEXT: xvsrarn.b.h $xr0, $xr0, $xr1 10; CHECK-NEXT: ret 11entry: 12 %res = call <32 x i8> @llvm.loongarch.lasx.xvsrarn.b.h(<16 x i16> %va, <16 x i16> %vb) 13 ret <32 x i8> %res 14} 15 16declare <16 x i16> @llvm.loongarch.lasx.xvsrarn.h.w(<8 x i32>, <8 x i32>) 17 18define <16 x i16> @lasx_xvsrarn_h_w(<8 x i32> %va, <8 x i32> %vb) nounwind { 19; CHECK-LABEL: lasx_xvsrarn_h_w: 20; CHECK: # %bb.0: # %entry 21; CHECK-NEXT: xvsrarn.h.w $xr0, $xr0, $xr1 22; CHECK-NEXT: ret 23entry: 24 %res = call <16 x i16> @llvm.loongarch.lasx.xvsrarn.h.w(<8 x i32> %va, <8 x i32> %vb) 25 ret <16 x i16> %res 26} 27 28declare <8 x i32> @llvm.loongarch.lasx.xvsrarn.w.d(<4 x i64>, <4 x i64>) 29 30define <8 x i32> @lasx_xvsrarn_w_d(<4 x i64> %va, <4 x i64> %vb) nounwind { 31; CHECK-LABEL: lasx_xvsrarn_w_d: 32; CHECK: # %bb.0: # %entry 33; CHECK-NEXT: xvsrarn.w.d $xr0, $xr0, $xr1 34; CHECK-NEXT: ret 35entry: 36 %res = call <8 x i32> @llvm.loongarch.lasx.xvsrarn.w.d(<4 x i64> %va, <4 x i64> %vb) 37 ret <8 x i32> %res 38} 39