1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s 3 4declare i32 @llvm.loongarch.lasx.xbz.v(<32 x i8>) 5 6define i32 @lasx_xbz_v(<32 x i8> %va) nounwind { 7; CHECK-LABEL: lasx_xbz_v: 8; CHECK: # %bb.0: # %entry 9; CHECK-NEXT: xvseteqz.v $fcc0, $xr0 10; CHECK-NEXT: bcnez $fcc0, .LBB0_2 11; CHECK-NEXT: # %bb.1: # %entry 12; CHECK-NEXT: addi.w $a0, $zero, 0 13; CHECK-NEXT: ret 14; CHECK-NEXT: .LBB0_2: # %entry 15; CHECK-NEXT: addi.w $a0, $zero, 1 16; CHECK-NEXT: ret 17entry: 18 %res = call i32 @llvm.loongarch.lasx.xbz.v(<32 x i8> %va) 19 ret i32 %res 20} 21 22declare i32 @llvm.loongarch.lasx.xbnz.v(<32 x i8>) 23 24define i32 @lasx_xbnz_v(<32 x i8> %va) nounwind { 25; CHECK-LABEL: lasx_xbnz_v: 26; CHECK: # %bb.0: # %entry 27; CHECK-NEXT: xvsetnez.v $fcc0, $xr0 28; CHECK-NEXT: bcnez $fcc0, .LBB1_2 29; CHECK-NEXT: # %bb.1: # %entry 30; CHECK-NEXT: addi.w $a0, $zero, 0 31; CHECK-NEXT: ret 32; CHECK-NEXT: .LBB1_2: # %entry 33; CHECK-NEXT: addi.w $a0, $zero, 1 34; CHECK-NEXT: ret 35entry: 36 %res = call i32 @llvm.loongarch.lasx.xbnz.v(<32 x i8> %va) 37 ret i32 %res 38} 39