xref: /llvm-project/llvm/test/CodeGen/LoongArch/lasx/intrinsic-msub.ll (revision 83311b2b5d1b9869f9a7b265994394ea898448a2) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
3
4declare <32 x i8> @llvm.loongarch.lasx.xvmsub.b(<32 x i8>, <32 x i8>, <32 x i8>)
5
6define <32 x i8> @lasx_xvmsub_b(<32 x i8> %va, <32 x i8> %vb, <32 x i8> %vc) nounwind {
7; CHECK-LABEL: lasx_xvmsub_b:
8; CHECK:       # %bb.0: # %entry
9; CHECK-NEXT:    xvmsub.b $xr0, $xr1, $xr2
10; CHECK-NEXT:    ret
11entry:
12  %res = call <32 x i8> @llvm.loongarch.lasx.xvmsub.b(<32 x i8> %va, <32 x i8> %vb, <32 x i8> %vc)
13  ret <32 x i8> %res
14}
15
16declare <16 x i16> @llvm.loongarch.lasx.xvmsub.h(<16 x i16>, <16 x i16>, <16 x i16>)
17
18define <16 x i16> @lasx_xvmsub_h(<16 x i16> %va, <16 x i16> %vb, <16 x i16> %vc) nounwind {
19; CHECK-LABEL: lasx_xvmsub_h:
20; CHECK:       # %bb.0: # %entry
21; CHECK-NEXT:    xvmsub.h $xr0, $xr1, $xr2
22; CHECK-NEXT:    ret
23entry:
24  %res = call <16 x i16> @llvm.loongarch.lasx.xvmsub.h(<16 x i16> %va, <16 x i16> %vb, <16 x i16> %vc)
25  ret <16 x i16> %res
26}
27
28declare <8 x i32> @llvm.loongarch.lasx.xvmsub.w(<8 x i32>, <8 x i32>, <8 x i32>)
29
30define <8 x i32> @lasx_xvmsub_w(<8 x i32> %va, <8 x i32> %vb, <8 x i32> %vc) nounwind {
31; CHECK-LABEL: lasx_xvmsub_w:
32; CHECK:       # %bb.0: # %entry
33; CHECK-NEXT:    xvmsub.w $xr0, $xr1, $xr2
34; CHECK-NEXT:    ret
35entry:
36  %res = call <8 x i32> @llvm.loongarch.lasx.xvmsub.w(<8 x i32> %va, <8 x i32> %vb, <8 x i32> %vc)
37  ret <8 x i32> %res
38}
39
40declare <4 x i64> @llvm.loongarch.lasx.xvmsub.d(<4 x i64>, <4 x i64>, <4 x i64>)
41
42define <4 x i64> @lasx_xvmsub_d(<4 x i64> %va, <4 x i64> %vb, <4 x i64> %vc) nounwind {
43; CHECK-LABEL: lasx_xvmsub_d:
44; CHECK:       # %bb.0: # %entry
45; CHECK-NEXT:    xvmsub.d $xr0, $xr1, $xr2
46; CHECK-NEXT:    ret
47entry:
48  %res = call <4 x i64> @llvm.loongarch.lasx.xvmsub.d(<4 x i64> %va, <4 x i64> %vb, <4 x i64> %vc)
49  ret <4 x i64> %res
50}
51