xref: /llvm-project/llvm/test/CodeGen/LoongArch/lasx/intrinsic-min.ll (revision 83311b2b5d1b9869f9a7b265994394ea898448a2) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
3
4declare <32 x i8> @llvm.loongarch.lasx.xvmin.b(<32 x i8>, <32 x i8>)
5
6define <32 x i8> @lasx_xvmin_b(<32 x i8> %va, <32 x i8> %vb) nounwind {
7; CHECK-LABEL: lasx_xvmin_b:
8; CHECK:       # %bb.0: # %entry
9; CHECK-NEXT:    xvmin.b $xr0, $xr0, $xr1
10; CHECK-NEXT:    ret
11entry:
12  %res = call <32 x i8> @llvm.loongarch.lasx.xvmin.b(<32 x i8> %va, <32 x i8> %vb)
13  ret <32 x i8> %res
14}
15
16declare <16 x i16> @llvm.loongarch.lasx.xvmin.h(<16 x i16>, <16 x i16>)
17
18define <16 x i16> @lasx_xvmin_h(<16 x i16> %va, <16 x i16> %vb) nounwind {
19; CHECK-LABEL: lasx_xvmin_h:
20; CHECK:       # %bb.0: # %entry
21; CHECK-NEXT:    xvmin.h $xr0, $xr0, $xr1
22; CHECK-NEXT:    ret
23entry:
24  %res = call <16 x i16> @llvm.loongarch.lasx.xvmin.h(<16 x i16> %va, <16 x i16> %vb)
25  ret <16 x i16> %res
26}
27
28declare <8 x i32> @llvm.loongarch.lasx.xvmin.w(<8 x i32>, <8 x i32>)
29
30define <8 x i32> @lasx_xvmin_w(<8 x i32> %va, <8 x i32> %vb) nounwind {
31; CHECK-LABEL: lasx_xvmin_w:
32; CHECK:       # %bb.0: # %entry
33; CHECK-NEXT:    xvmin.w $xr0, $xr0, $xr1
34; CHECK-NEXT:    ret
35entry:
36  %res = call <8 x i32> @llvm.loongarch.lasx.xvmin.w(<8 x i32> %va, <8 x i32> %vb)
37  ret <8 x i32> %res
38}
39
40declare <4 x i64> @llvm.loongarch.lasx.xvmin.d(<4 x i64>, <4 x i64>)
41
42define <4 x i64> @lasx_xvmin_d(<4 x i64> %va, <4 x i64> %vb) nounwind {
43; CHECK-LABEL: lasx_xvmin_d:
44; CHECK:       # %bb.0: # %entry
45; CHECK-NEXT:    xvmin.d $xr0, $xr0, $xr1
46; CHECK-NEXT:    ret
47entry:
48  %res = call <4 x i64> @llvm.loongarch.lasx.xvmin.d(<4 x i64> %va, <4 x i64> %vb)
49  ret <4 x i64> %res
50}
51
52declare <32 x i8> @llvm.loongarch.lasx.xvmini.b(<32 x i8>, i32)
53
54define <32 x i8> @lasx_xvmini_b(<32 x i8> %va) nounwind {
55; CHECK-LABEL: lasx_xvmini_b:
56; CHECK:       # %bb.0: # %entry
57; CHECK-NEXT:    xvmini.b $xr0, $xr0, 1
58; CHECK-NEXT:    ret
59entry:
60  %res = call <32 x i8> @llvm.loongarch.lasx.xvmini.b(<32 x i8> %va, i32 1)
61  ret <32 x i8> %res
62}
63
64declare <16 x i16> @llvm.loongarch.lasx.xvmini.h(<16 x i16>, i32)
65
66define <16 x i16> @lasx_xvmini_h(<16 x i16> %va) nounwind {
67; CHECK-LABEL: lasx_xvmini_h:
68; CHECK:       # %bb.0: # %entry
69; CHECK-NEXT:    xvmini.h $xr0, $xr0, 1
70; CHECK-NEXT:    ret
71entry:
72  %res = call <16 x i16> @llvm.loongarch.lasx.xvmini.h(<16 x i16> %va, i32 1)
73  ret <16 x i16> %res
74}
75
76declare <8 x i32> @llvm.loongarch.lasx.xvmini.w(<8 x i32>, i32)
77
78define <8 x i32> @lasx_xvmini_w(<8 x i32> %va) nounwind {
79; CHECK-LABEL: lasx_xvmini_w:
80; CHECK:       # %bb.0: # %entry
81; CHECK-NEXT:    xvmini.w $xr0, $xr0, 1
82; CHECK-NEXT:    ret
83entry:
84  %res = call <8 x i32> @llvm.loongarch.lasx.xvmini.w(<8 x i32> %va, i32 1)
85  ret <8 x i32> %res
86}
87
88declare <4 x i64> @llvm.loongarch.lasx.xvmini.d(<4 x i64>, i32)
89
90define <4 x i64> @lasx_xvmini_d(<4 x i64> %va) nounwind {
91; CHECK-LABEL: lasx_xvmini_d:
92; CHECK:       # %bb.0: # %entry
93; CHECK-NEXT:    xvmini.d $xr0, $xr0, 1
94; CHECK-NEXT:    ret
95entry:
96  %res = call <4 x i64> @llvm.loongarch.lasx.xvmini.d(<4 x i64> %va, i32 1)
97  ret <4 x i64> %res
98}
99
100declare <32 x i8> @llvm.loongarch.lasx.xvmin.bu(<32 x i8>, <32 x i8>)
101
102define <32 x i8> @lasx_xvmin_bu(<32 x i8> %va, <32 x i8> %vb) nounwind {
103; CHECK-LABEL: lasx_xvmin_bu:
104; CHECK:       # %bb.0: # %entry
105; CHECK-NEXT:    xvmin.bu $xr0, $xr0, $xr1
106; CHECK-NEXT:    ret
107entry:
108  %res = call <32 x i8> @llvm.loongarch.lasx.xvmin.bu(<32 x i8> %va, <32 x i8> %vb)
109  ret <32 x i8> %res
110}
111
112declare <16 x i16> @llvm.loongarch.lasx.xvmin.hu(<16 x i16>, <16 x i16>)
113
114define <16 x i16> @lasx_xvmin_hu(<16 x i16> %va, <16 x i16> %vb) nounwind {
115; CHECK-LABEL: lasx_xvmin_hu:
116; CHECK:       # %bb.0: # %entry
117; CHECK-NEXT:    xvmin.hu $xr0, $xr0, $xr1
118; CHECK-NEXT:    ret
119entry:
120  %res = call <16 x i16> @llvm.loongarch.lasx.xvmin.hu(<16 x i16> %va, <16 x i16> %vb)
121  ret <16 x i16> %res
122}
123
124declare <8 x i32> @llvm.loongarch.lasx.xvmin.wu(<8 x i32>, <8 x i32>)
125
126define <8 x i32> @lasx_xvmin_wu(<8 x i32> %va, <8 x i32> %vb) nounwind {
127; CHECK-LABEL: lasx_xvmin_wu:
128; CHECK:       # %bb.0: # %entry
129; CHECK-NEXT:    xvmin.wu $xr0, $xr0, $xr1
130; CHECK-NEXT:    ret
131entry:
132  %res = call <8 x i32> @llvm.loongarch.lasx.xvmin.wu(<8 x i32> %va, <8 x i32> %vb)
133  ret <8 x i32> %res
134}
135
136declare <4 x i64> @llvm.loongarch.lasx.xvmin.du(<4 x i64>, <4 x i64>)
137
138define <4 x i64> @lasx_xvmin_du(<4 x i64> %va, <4 x i64> %vb) nounwind {
139; CHECK-LABEL: lasx_xvmin_du:
140; CHECK:       # %bb.0: # %entry
141; CHECK-NEXT:    xvmin.du $xr0, $xr0, $xr1
142; CHECK-NEXT:    ret
143entry:
144  %res = call <4 x i64> @llvm.loongarch.lasx.xvmin.du(<4 x i64> %va, <4 x i64> %vb)
145  ret <4 x i64> %res
146}
147
148declare <32 x i8> @llvm.loongarch.lasx.xvmini.bu(<32 x i8>, i32)
149
150define <32 x i8> @lasx_xvmini_bu(<32 x i8> %va) nounwind {
151; CHECK-LABEL: lasx_xvmini_bu:
152; CHECK:       # %bb.0: # %entry
153; CHECK-NEXT:    xvmini.bu $xr0, $xr0, 1
154; CHECK-NEXT:    ret
155entry:
156  %res = call <32 x i8> @llvm.loongarch.lasx.xvmini.bu(<32 x i8> %va, i32 1)
157  ret <32 x i8> %res
158}
159
160declare <16 x i16> @llvm.loongarch.lasx.xvmini.hu(<16 x i16>, i32)
161
162define <16 x i16> @lasx_xvmini_hu(<16 x i16> %va) nounwind {
163; CHECK-LABEL: lasx_xvmini_hu:
164; CHECK:       # %bb.0: # %entry
165; CHECK-NEXT:    xvmini.hu $xr0, $xr0, 1
166; CHECK-NEXT:    ret
167entry:
168  %res = call <16 x i16> @llvm.loongarch.lasx.xvmini.hu(<16 x i16> %va, i32 1)
169  ret <16 x i16> %res
170}
171
172declare <8 x i32> @llvm.loongarch.lasx.xvmini.wu(<8 x i32>, i32)
173
174define <8 x i32> @lasx_xvmini_wu(<8 x i32> %va) nounwind {
175; CHECK-LABEL: lasx_xvmini_wu:
176; CHECK:       # %bb.0: # %entry
177; CHECK-NEXT:    xvmini.wu $xr0, $xr0, 1
178; CHECK-NEXT:    ret
179entry:
180  %res = call <8 x i32> @llvm.loongarch.lasx.xvmini.wu(<8 x i32> %va, i32 1)
181  ret <8 x i32> %res
182}
183
184declare <4 x i64> @llvm.loongarch.lasx.xvmini.du(<4 x i64>, i32)
185
186define <4 x i64> @lasx_xvmini_du(<4 x i64> %va) nounwind {
187; CHECK-LABEL: lasx_xvmini_du:
188; CHECK:       # %bb.0: # %entry
189; CHECK-NEXT:    xvmini.du $xr0, $xr0, 1
190; CHECK-NEXT:    ret
191entry:
192  %res = call <4 x i64> @llvm.loongarch.lasx.xvmini.du(<4 x i64> %va, i32 1)
193  ret <4 x i64> %res
194}
195