1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s 3 4declare <32 x i8> @llvm.loongarch.lasx.xvextrins.b(<32 x i8>, <32 x i8>, i32) 5 6define <32 x i8> @lasx_xvextrins_b(<32 x i8> %va, <32 x i8> %vb) nounwind { 7; CHECK-LABEL: lasx_xvextrins_b: 8; CHECK: # %bb.0: # %entry 9; CHECK-NEXT: xvextrins.b $xr0, $xr1, 1 10; CHECK-NEXT: ret 11entry: 12 %res = call <32 x i8> @llvm.loongarch.lasx.xvextrins.b(<32 x i8> %va, <32 x i8> %vb, i32 1) 13 ret <32 x i8> %res 14} 15 16declare <16 x i16> @llvm.loongarch.lasx.xvextrins.h(<16 x i16>, <16 x i16>, i32) 17 18define <16 x i16> @lasx_xvextrins_h(<16 x i16> %va, <16 x i16> %vb) nounwind { 19; CHECK-LABEL: lasx_xvextrins_h: 20; CHECK: # %bb.0: # %entry 21; CHECK-NEXT: xvextrins.h $xr0, $xr1, 1 22; CHECK-NEXT: ret 23entry: 24 %res = call <16 x i16> @llvm.loongarch.lasx.xvextrins.h(<16 x i16> %va, <16 x i16> %vb, i32 1) 25 ret <16 x i16> %res 26} 27 28declare <8 x i32> @llvm.loongarch.lasx.xvextrins.w(<8 x i32>, <8 x i32>, i32) 29 30define <8 x i32> @lasx_xvextrins_w(<8 x i32> %va, <8 x i32> %vb) nounwind { 31; CHECK-LABEL: lasx_xvextrins_w: 32; CHECK: # %bb.0: # %entry 33; CHECK-NEXT: xvextrins.w $xr0, $xr1, 1 34; CHECK-NEXT: ret 35entry: 36 %res = call <8 x i32> @llvm.loongarch.lasx.xvextrins.w(<8 x i32> %va, <8 x i32> %vb, i32 1) 37 ret <8 x i32> %res 38} 39 40declare <4 x i64> @llvm.loongarch.lasx.xvextrins.d(<4 x i64>, <4 x i64>, i32) 41 42define <4 x i64> @lasx_xvextrins_d(<4 x i64> %va, <4 x i64> %vb) nounwind { 43; CHECK-LABEL: lasx_xvextrins_d: 44; CHECK: # %bb.0: # %entry 45; CHECK-NEXT: xvextrins.d $xr0, $xr1, 1 46; CHECK-NEXT: ret 47entry: 48 %res = call <4 x i64> @llvm.loongarch.lasx.xvextrins.d(<4 x i64> %va, <4 x i64> %vb, i32 1) 49 ret <4 x i64> %res 50} 51