xref: /llvm-project/llvm/test/CodeGen/LoongArch/lasx/intrinsic-clz.ll (revision 83311b2b5d1b9869f9a7b265994394ea898448a2) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
3
4declare <32 x i8> @llvm.loongarch.lasx.xvclz.b(<32 x i8>)
5
6define <32 x i8> @lasx_xvclz_b(<32 x i8> %va) nounwind {
7; CHECK-LABEL: lasx_xvclz_b:
8; CHECK:       # %bb.0: # %entry
9; CHECK-NEXT:    xvclz.b $xr0, $xr0
10; CHECK-NEXT:    ret
11entry:
12  %res = call <32 x i8> @llvm.loongarch.lasx.xvclz.b(<32 x i8> %va)
13  ret <32 x i8> %res
14}
15
16declare <16 x i16> @llvm.loongarch.lasx.xvclz.h(<16 x i16>)
17
18define <16 x i16> @lasx_xvclz_h(<16 x i16> %va) nounwind {
19; CHECK-LABEL: lasx_xvclz_h:
20; CHECK:       # %bb.0: # %entry
21; CHECK-NEXT:    xvclz.h $xr0, $xr0
22; CHECK-NEXT:    ret
23entry:
24  %res = call <16 x i16> @llvm.loongarch.lasx.xvclz.h(<16 x i16> %va)
25  ret <16 x i16> %res
26}
27
28declare <8 x i32> @llvm.loongarch.lasx.xvclz.w(<8 x i32>)
29
30define <8 x i32> @lasx_xvclz_w(<8 x i32> %va) nounwind {
31; CHECK-LABEL: lasx_xvclz_w:
32; CHECK:       # %bb.0: # %entry
33; CHECK-NEXT:    xvclz.w $xr0, $xr0
34; CHECK-NEXT:    ret
35entry:
36  %res = call <8 x i32> @llvm.loongarch.lasx.xvclz.w(<8 x i32> %va)
37  ret <8 x i32> %res
38}
39
40declare <4 x i64> @llvm.loongarch.lasx.xvclz.d(<4 x i64>)
41
42define <4 x i64> @lasx_xvclz_d(<4 x i64> %va) nounwind {
43; CHECK-LABEL: lasx_xvclz_d:
44; CHECK:       # %bb.0: # %entry
45; CHECK-NEXT:    xvclz.d $xr0, $xr0
46; CHECK-NEXT:    ret
47entry:
48  %res = call <4 x i64> @llvm.loongarch.lasx.xvclz.d(<4 x i64> %va)
49  ret <4 x i64> %res
50}
51