1# RUN: llc -run-pass=peephole-opt %s -o - | FileCheck %s 2# RUN: llc -passes=peephole-opt %s -o - | FileCheck %s 3 4# Test the compare fold peephole. 5 6# CHECK-LABEL: name: test0a 7# TODO: Enhance combiner to handle this case. This expands into: 8# sub $r7, $r6, $r3 9# sub.f $r7, $r6, $r0 10# sel.eq $r18, $r3, $rv 11# This is different from the pattern currently matched. If the lowered form had 12# been sub.f $r3, 0, $r0 then it would have matched. 13 14# CHECK-LABEL: name: test1a 15# CHECK: [[IN1:%.*]]:gpr = COPY $r7 16# CHECK: [[IN2:%.*]]:gpr = COPY $r6 17# CHECK: SUB_F_R [[IN1]], [[IN2]], 0, implicit-def $sr 18 19# CHECK-LABEL: name: test1b 20# CHECK: [[IN1:%.*]]:gpr = COPY $r7 21# CHECK: [[IN2:%.*]]:gpr = COPY $r6 22# CHECK: SUB_F_R [[IN1]], [[IN2]], 0, implicit-def $sr 23 24# CHECK-LABEL: name: test2a 25# CHECK: [[IN1:%.*]]:gpr = COPY $r7 26# CHECK: [[IN2:%.*]]:gpr = COPY $r6 27# CHECK: SUB_F_R [[IN1]], [[IN2]], 0, implicit-def $sr 28 29# CHECK-LABEL: name: test2b 30# CHECK: [[IN1:%.*]]:gpr = COPY $r7 31# CHECK: [[IN2:%.*]]:gpr = COPY $r6 32# CHECK: SUB_F_R [[IN1]], [[IN2]], 0, implicit-def $sr 33 34# CHECK-LABEL: name: test3 35# CHECK: AND_F_R 36# CHECK: AND_F_R 37# CHECK: AND_F_R 38 39--- | 40 target datalayout = "E-m:e-p:32:32-i64:64-a:0:32-n32-S64" 41 target triple = "lanai-unknown-unknown" 42 43 @a = global i32 -1, align 4 44 @b = global i32 0, align 4 45 46 define i32 @test0a(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) { 47 entry: 48 %sub = sub i32 %b, %a 49 %cmp = icmp eq i32 %sub, 0 50 %cond = select i1 %cmp, i32 %c, i32 %sub 51 ret i32 %cond 52 } 53 54 define i32 @test0b(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) { 55 entry: 56 %cmp = icmp eq i32 %b, %a 57 %cond = select i1 %cmp, i32 %c, i32 %b 58 ret i32 %cond 59 } 60 61 define i32 @test1a(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) { 62 entry: 63 %sub = sub i32 %b, %a 64 %cmp = icmp slt i32 %sub, 0 65 %cond = select i1 %cmp, i32 %c, i32 %d 66 ret i32 %cond 67 } 68 69 define i32 @test1b(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) { 70 entry: 71 %sub = sub i32 %b, %a 72 %cmp = icmp slt i32 %sub, 0 73 %cond = select i1 %cmp, i32 %c, i32 %d 74 ret i32 %cond 75 } 76 77 define i32 @test2a(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) { 78 entry: 79 %sub = sub i32 %b, %a 80 %cmp = icmp sgt i32 %sub, -1 81 %cond = select i1 %cmp, i32 %c, i32 %d 82 ret i32 %cond 83 } 84 85 define i32 @test2b(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) { 86 entry: 87 %sub = sub i32 %b, %a 88 %cmp = icmp sgt i32 %sub, -1 89 %cond = select i1 %cmp, i32 %c, i32 %d 90 ret i32 %cond 91 } 92 93 define i32 @test3(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) { 94 entry: 95 %sub = sub i32 %b, %a 96 %cmp = icmp slt i32 %sub, 1 97 %cond = select i1 %cmp, i32 %c, i32 %d 98 ret i32 %cond 99 } 100 101 define i32 @test4(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) { 102 entry: 103 %cmp = icmp ne i32 %a, 0 104 %cmp1 = icmp ult i32 %a, %b 105 %or.cond = and i1 %cmp, %cmp1 106 br i1 %or.cond, label %return, label %if.end 107 108 if.end: ; preds = %entry 109 %cmp2 = icmp ne i32 %b, 0 110 %cmp4 = icmp ult i32 %b, %c 111 %or.cond29 = and i1 %cmp2, %cmp4 112 br i1 %or.cond29, label %return, label %if.end6 113 114 if.end6: ; preds = %if.end 115 %cmp7 = icmp ne i32 %c, 0 116 %cmp9 = icmp ult i32 %c, %d 117 %or.cond30 = and i1 %cmp7, %cmp9 118 br i1 %or.cond30, label %return, label %if.end11 119 120 if.end11: ; preds = %if.end6 121 %cmp12 = icmp ne i32 %d, 0 122 %cmp14 = icmp ult i32 %d, %a 123 %or.cond31 = and i1 %cmp12, %cmp14 124 %b. = select i1 %or.cond31, i32 %b, i32 21 125 ret i32 %b. 126 127 return: ; preds = %if.end6, %if.end, %entry 128 %retval.0 = phi i32 [ %c, %entry ], [ %d, %if.end ], [ %a, %if.end6 ] 129 ret i32 %retval.0 130 } 131 132 define void @testBB() { 133 entry: 134 %0 = load i32, ptr @a, align 4, !tbaa !0 135 %1 = load i32, ptr @b, align 4, !tbaa !0 136 %sub.i = sub i32 %1, %0 137 %tobool = icmp sgt i32 %sub.i, -1 138 br i1 %tobool, label %if.end, label %if.then 139 140 if.then: ; preds = %entry 141 %call1 = tail call i32 @g() 142 br label %while.body 143 144 while.body: ; preds = %while.body, %if.then 145 br label %while.body 146 147 if.end: ; preds = %entry 148 %cmp.i = icmp slt i32 %sub.i, 1 149 br i1 %cmp.i, label %if.then4, label %if.end7 150 151 if.then4: ; preds = %if.end 152 %call5 = tail call i32 @g() 153 br label %while.body6 154 155 while.body6: ; preds = %while.body6, %if.then4 156 br label %while.body6 157 158 if.end7: ; preds = %if.end 159 ret void 160 } 161 162 declare i32 @g(...) 163 164 ; Function Attrs: nounwind 165 declare void @llvm.stackprotector(ptr, ptr) #0 166 167 attributes #0 = { nounwind } 168 169 !0 = !{!1, !1, i64 0} 170 !1 = !{!"int", !2, i64 0} 171 !2 = !{!"omnipotent char", !3, i64 0} 172 !3 = !{!"Simple C/C++ TBAA"} 173 174... 175--- 176name: test0a 177alignment: 4 178exposesReturnsTwice: false 179tracksRegLiveness: true 180registers: 181 - { id: 0, class: gpr } 182 - { id: 1, class: gpr } 183 - { id: 2, class: gpr } 184 - { id: 3, class: gpr } 185 - { id: 4, class: gpr } 186 - { id: 5, class: gpr } 187liveins: 188 - { reg: '$r6', virtual-reg: '%0' } 189 - { reg: '$r7', virtual-reg: '%1' } 190 - { reg: '$r18', virtual-reg: '%2' } 191frameInfo: 192 isFrameAddressTaken: false 193 isReturnAddressTaken: false 194 hasStackMap: false 195 hasPatchPoint: false 196 stackSize: 0 197 offsetAdjustment: 0 198 maxAlignment: 0 199 adjustsStack: false 200 hasCalls: false 201 maxCallFrameSize: 0 202 hasOpaqueSPAdjustment: false 203 hasVAStart: false 204 hasMustTailInVarArgFunc: false 205body: | 206 bb.0.entry: 207 liveins: $r6, $r7, $r18 208 209 %2 = COPY $r18 210 %1 = COPY $r7 211 %0 = COPY $r6 212 %4 = SUB_R %1, %0, 0 213 SFSUB_F_RI_LO %4, 0, implicit-def $sr 214 %5 = SELECT %2, %4, 7, implicit $sr 215 $rv = COPY %5 216 RET implicit $rca, implicit $rv 217 218... 219--- 220name: test0b 221alignment: 4 222exposesReturnsTwice: false 223tracksRegLiveness: true 224registers: 225 - { id: 0, class: gpr } 226 - { id: 1, class: gpr } 227 - { id: 2, class: gpr } 228 - { id: 3, class: gpr } 229 - { id: 4, class: gpr } 230liveins: 231 - { reg: '$r6', virtual-reg: '%0' } 232 - { reg: '$r7', virtual-reg: '%1' } 233 - { reg: '$r18', virtual-reg: '%2' } 234frameInfo: 235 isFrameAddressTaken: false 236 isReturnAddressTaken: false 237 hasStackMap: false 238 hasPatchPoint: false 239 stackSize: 0 240 offsetAdjustment: 0 241 maxAlignment: 0 242 adjustsStack: false 243 hasCalls: false 244 maxCallFrameSize: 0 245 hasOpaqueSPAdjustment: false 246 hasVAStart: false 247 hasMustTailInVarArgFunc: false 248body: | 249 bb.0.entry: 250 liveins: $r6, $r7, $r18 251 252 %2 = COPY $r18 253 %1 = COPY $r7 254 %0 = COPY $r6 255 SFSUB_F_RR %1, %0, implicit-def $sr 256 %4 = SELECT %2, %1, 7, implicit $sr 257 $rv = COPY %4 258 RET implicit $rca, implicit $rv 259 260... 261--- 262name: test1a 263alignment: 4 264exposesReturnsTwice: false 265tracksRegLiveness: true 266registers: 267 - { id: 0, class: gpr } 268 - { id: 1, class: gpr } 269 - { id: 2, class: gpr } 270 - { id: 3, class: gpr } 271 - { id: 4, class: gpr } 272 - { id: 5, class: gpr } 273liveins: 274 - { reg: '$r6', virtual-reg: '%0' } 275 - { reg: '$r7', virtual-reg: '%1' } 276 - { reg: '$r18', virtual-reg: '%2' } 277 - { reg: '$r19', virtual-reg: '%3' } 278frameInfo: 279 isFrameAddressTaken: false 280 isReturnAddressTaken: false 281 hasStackMap: false 282 hasPatchPoint: false 283 stackSize: 0 284 offsetAdjustment: 0 285 maxAlignment: 0 286 adjustsStack: false 287 hasCalls: false 288 maxCallFrameSize: 0 289 hasOpaqueSPAdjustment: false 290 hasVAStart: false 291 hasMustTailInVarArgFunc: false 292body: | 293 bb.0.entry: 294 liveins: $r6, $r7, $r18, $r19 295 296 %3 = COPY $r19 297 %2 = COPY $r18 298 %1 = COPY $r7 299 %0 = COPY $r6 300 %4 = SUB_R %1, %0, 0 301 SFSUB_F_RI_LO killed %4, 0, implicit-def $sr 302 %5 = SELECT %2, %3, 11, implicit $sr 303 $rv = COPY %5 304 RET implicit $rca, implicit $rv 305 306... 307--- 308name: test1b 309alignment: 4 310exposesReturnsTwice: false 311tracksRegLiveness: true 312registers: 313 - { id: 0, class: gpr } 314 - { id: 1, class: gpr } 315 - { id: 2, class: gpr } 316 - { id: 3, class: gpr } 317 - { id: 4, class: gpr } 318 - { id: 5, class: gpr } 319liveins: 320 - { reg: '$r6', virtual-reg: '%0' } 321 - { reg: '$r7', virtual-reg: '%1' } 322 - { reg: '$r18', virtual-reg: '%2' } 323 - { reg: '$r19', virtual-reg: '%3' } 324frameInfo: 325 isFrameAddressTaken: false 326 isReturnAddressTaken: false 327 hasStackMap: false 328 hasPatchPoint: false 329 stackSize: 0 330 offsetAdjustment: 0 331 maxAlignment: 0 332 adjustsStack: false 333 hasCalls: false 334 maxCallFrameSize: 0 335 hasOpaqueSPAdjustment: false 336 hasVAStart: false 337 hasMustTailInVarArgFunc: false 338body: | 339 bb.0.entry: 340 liveins: $r6, $r7, $r18, $r19 341 342 %3 = COPY $r19 343 %2 = COPY $r18 344 %1 = COPY $r7 345 %0 = COPY $r6 346 %4 = SUB_R %1, %0, 0 347 SFSUB_F_RI_LO killed %4, 0, implicit-def $sr 348 %5 = SELECT %2, %3, 11, implicit $sr 349 $rv = COPY %5 350 RET implicit $rca, implicit $rv 351 352... 353--- 354name: test2a 355alignment: 4 356exposesReturnsTwice: false 357tracksRegLiveness: true 358registers: 359 - { id: 0, class: gpr } 360 - { id: 1, class: gpr } 361 - { id: 2, class: gpr } 362 - { id: 3, class: gpr } 363 - { id: 4, class: gpr } 364 - { id: 5, class: gpr } 365liveins: 366 - { reg: '$r6', virtual-reg: '%0' } 367 - { reg: '$r7', virtual-reg: '%1' } 368 - { reg: '$r18', virtual-reg: '%2' } 369 - { reg: '$r19', virtual-reg: '%3' } 370frameInfo: 371 isFrameAddressTaken: false 372 isReturnAddressTaken: false 373 hasStackMap: false 374 hasPatchPoint: false 375 stackSize: 0 376 offsetAdjustment: 0 377 maxAlignment: 0 378 adjustsStack: false 379 hasCalls: false 380 maxCallFrameSize: 0 381 hasOpaqueSPAdjustment: false 382 hasVAStart: false 383 hasMustTailInVarArgFunc: false 384body: | 385 bb.0.entry: 386 liveins: $r6, $r7, $r18, $r19 387 388 %3 = COPY $r19 389 %2 = COPY $r18 390 %1 = COPY $r7 391 %0 = COPY $r6 392 %4 = SUB_R %1, %0, 0 393 SFSUB_F_RI_LO killed %4, 0, implicit-def $sr 394 %5 = SELECT %2, %3, 10, implicit $sr 395 $rv = COPY %5 396 RET implicit $rca, implicit $rv 397 398... 399--- 400name: test2b 401alignment: 4 402exposesReturnsTwice: false 403tracksRegLiveness: true 404registers: 405 - { id: 0, class: gpr } 406 - { id: 1, class: gpr } 407 - { id: 2, class: gpr } 408 - { id: 3, class: gpr } 409 - { id: 4, class: gpr } 410 - { id: 5, class: gpr } 411liveins: 412 - { reg: '$r6', virtual-reg: '%0' } 413 - { reg: '$r7', virtual-reg: '%1' } 414 - { reg: '$r18', virtual-reg: '%2' } 415 - { reg: '$r19', virtual-reg: '%3' } 416frameInfo: 417 isFrameAddressTaken: false 418 isReturnAddressTaken: false 419 hasStackMap: false 420 hasPatchPoint: false 421 stackSize: 0 422 offsetAdjustment: 0 423 maxAlignment: 0 424 adjustsStack: false 425 hasCalls: false 426 maxCallFrameSize: 0 427 hasOpaqueSPAdjustment: false 428 hasVAStart: false 429 hasMustTailInVarArgFunc: false 430body: | 431 bb.0.entry: 432 liveins: $r6, $r7, $r18, $r19 433 434 %3 = COPY $r19 435 %2 = COPY $r18 436 %1 = COPY $r7 437 %0 = COPY $r6 438 %4 = SUB_R %1, %0, 0 439 SFSUB_F_RI_LO killed %4, 0, implicit-def $sr 440 %5 = SELECT %2, %3, 10, implicit $sr 441 $rv = COPY %5 442 RET implicit $rca, implicit $rv 443 444... 445--- 446name: test3 447alignment: 4 448exposesReturnsTwice: false 449tracksRegLiveness: true 450registers: 451 - { id: 0, class: gpr } 452 - { id: 1, class: gpr } 453 - { id: 2, class: gpr } 454 - { id: 3, class: gpr } 455 - { id: 4, class: gpr } 456 - { id: 5, class: gpr } 457liveins: 458 - { reg: '$r6', virtual-reg: '%0' } 459 - { reg: '$r7', virtual-reg: '%1' } 460 - { reg: '$r18', virtual-reg: '%2' } 461 - { reg: '$r19', virtual-reg: '%3' } 462frameInfo: 463 isFrameAddressTaken: false 464 isReturnAddressTaken: false 465 hasStackMap: false 466 hasPatchPoint: false 467 stackSize: 0 468 offsetAdjustment: 0 469 maxAlignment: 0 470 adjustsStack: false 471 hasCalls: false 472 maxCallFrameSize: 0 473 hasOpaqueSPAdjustment: false 474 hasVAStart: false 475 hasMustTailInVarArgFunc: false 476body: | 477 bb.0.entry: 478 liveins: $r6, $r7, $r18, $r19 479 480 %3 = COPY $r19 481 %2 = COPY $r18 482 %1 = COPY $r7 483 %0 = COPY $r6 484 %4 = SUB_R %1, %0, 0 485 SFSUB_F_RI_LO killed %4, 1, implicit-def $sr 486 %5 = SELECT %2, %3, 13, implicit $sr 487 $rv = COPY %5 488 RET implicit $rca, implicit $rv 489 490... 491--- 492name: test4 493alignment: 4 494exposesReturnsTwice: false 495tracksRegLiveness: true 496registers: 497 - { id: 0, class: gpr } 498 - { id: 1, class: gpr } 499 - { id: 2, class: gpr } 500 - { id: 3, class: gpr } 501 - { id: 4, class: gpr } 502 - { id: 5, class: gpr } 503 - { id: 6, class: gpr } 504 - { id: 7, class: gpr } 505 - { id: 8, class: gpr } 506 - { id: 9, class: gpr } 507 - { id: 10, class: gpr } 508 - { id: 11, class: gpr } 509 - { id: 12, class: gpr } 510 - { id: 13, class: gpr } 511 - { id: 14, class: gpr } 512 - { id: 15, class: gpr } 513 - { id: 16, class: gpr } 514 - { id: 17, class: gpr } 515 - { id: 18, class: gpr } 516 - { id: 19, class: gpr } 517 - { id: 20, class: gpr } 518 - { id: 21, class: gpr } 519 - { id: 22, class: gpr } 520liveins: 521 - { reg: '$r6', virtual-reg: '%1' } 522 - { reg: '$r7', virtual-reg: '%2' } 523 - { reg: '$r18', virtual-reg: '%3' } 524 - { reg: '$r19', virtual-reg: '%4' } 525frameInfo: 526 isFrameAddressTaken: false 527 isReturnAddressTaken: false 528 hasStackMap: false 529 hasPatchPoint: false 530 stackSize: 0 531 offsetAdjustment: 0 532 maxAlignment: 0 533 adjustsStack: false 534 hasCalls: false 535 maxCallFrameSize: 0 536 hasOpaqueSPAdjustment: false 537 hasVAStart: false 538 hasMustTailInVarArgFunc: false 539body: | 540 bb.0.entry: 541 successors: %bb.4.return, %bb.1.if.end 542 liveins: $r6, $r7, $r18, $r19 543 544 %4 = COPY $r19 545 %3 = COPY $r18 546 %2 = COPY $r7 547 %1 = COPY $r6 548 SFSUB_F_RI_LO %1, 0, implicit-def $sr 549 %5 = SCC 6, implicit $sr 550 SFSUB_F_RR %1, %2, implicit-def $sr 551 %6 = SCC 4, implicit $sr 552 %7 = AND_R killed %5, killed %6, 0 553 %8 = SLI 1 554 %9 = AND_R killed %7, %8, 0 555 SFSUB_F_RI_LO killed %9, 0, implicit-def $sr 556 BRCC %bb.4.return, 6, implicit $sr 557 BT %bb.1.if.end 558 559 bb.1.if.end: 560 successors: %bb.4.return, %bb.2.if.end6 561 562 SFSUB_F_RI_LO %2, 0, implicit-def $sr 563 %10 = SCC 6, implicit $sr 564 SFSUB_F_RR %2, %3, implicit-def $sr 565 %11 = SCC 4, implicit $sr 566 %12 = AND_R killed %10, killed %11, 0 567 %14 = AND_R killed %12, %8, 0 568 SFSUB_F_RI_LO killed %14, 0, implicit-def $sr 569 BRCC %bb.4.return, 6, implicit $sr 570 BT %bb.2.if.end6 571 572 bb.2.if.end6: 573 successors: %bb.4.return, %bb.3.if.end11 574 575 SFSUB_F_RI_LO %3, 0, implicit-def $sr 576 %15 = SCC 6, implicit $sr 577 SFSUB_F_RR %3, %4, implicit-def $sr 578 %16 = SCC 4, implicit $sr 579 %17 = AND_R killed %15, killed %16, 0 580 %18 = SLI 1 581 %19 = AND_R killed %17, killed %18, 0 582 SFSUB_F_RI_LO killed %19, 0, implicit-def $sr 583 BRCC %bb.4.return, 6, implicit $sr 584 BT %bb.3.if.end11 585 586 bb.3.if.end11: 587 %20 = SLI 21 588 SFSUB_F_RR %4, %1, implicit-def $sr 589 %21 = SELECT %2, %20, 4, implicit $sr 590 SFSUB_F_RI_LO %4, 0, implicit-def $sr 591 %22 = SELECT killed %21, %20, 6, implicit $sr 592 $rv = COPY %22 593 RET implicit $rca, implicit $rv 594 595 bb.4.return: 596 %0 = PHI %3, %bb.0.entry, %4, %bb.1.if.end, %1, %bb.2.if.end6 597 $rv = COPY %0 598 RET implicit $rca, implicit $rv 599 600... 601--- 602name: testBB 603alignment: 4 604exposesReturnsTwice: false 605tracksRegLiveness: true 606registers: 607 - { id: 0, class: gpr } 608 - { id: 1, class: gpr } 609 - { id: 2, class: gpr } 610 - { id: 3, class: gpr } 611 - { id: 4, class: gpr } 612 - { id: 5, class: gpr } 613 - { id: 6, class: gpr } 614 - { id: 7, class: gpr } 615 - { id: 8, class: gpr } 616frameInfo: 617 isFrameAddressTaken: false 618 isReturnAddressTaken: false 619 hasStackMap: false 620 hasPatchPoint: false 621 stackSize: 0 622 offsetAdjustment: 0 623 maxAlignment: 0 624 adjustsStack: false 625 hasCalls: true 626 maxCallFrameSize: 0 627 hasOpaqueSPAdjustment: false 628 hasVAStart: false 629 hasMustTailInVarArgFunc: false 630body: | 631 bb.0.entry: 632 successors: %bb.3.if.end, %bb.1.if.then 633 634 %1 = MOVHI target-flags(lanai-hi) @a 635 %2 = OR_I_LO killed %1, target-flags(lanai-lo) @a 636 %3 = LDW_RI killed %2, 0, 0 :: (load (s32) from @a, !tbaa !0) 637 %4 = MOVHI target-flags(lanai-hi) @b 638 %5 = OR_I_LO killed %4, target-flags(lanai-lo) @b 639 %6 = LDW_RI killed %5, 0, 0 :: (load (s32) from @b, !tbaa !0) 640 %0 = SUB_R killed %6, killed %3, 0 641 SFSUB_F_RI_LO %0, 0, implicit-def $sr 642 BRCC %bb.3.if.end, 10, implicit $sr 643 BT %bb.1.if.then 644 645 bb.1.if.then: 646 successors: %bb.2.while.body 647 648 ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp 649 CALL @g, csr, implicit-def dead $rca, implicit $sp, implicit-def $sp, implicit-def $rv 650 ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp 651 652 bb.2.while.body: 653 successors: %bb.2.while.body 654 655 BT %bb.2.while.body 656 657 bb.3.if.end: 658 successors: %bb.4.if.then4, %bb.6.if.end7 659 liveins: $sr 660 661 BRCC %bb.6.if.end7, 14, implicit $sr 662 BT %bb.4.if.then4 663 664 bb.4.if.then4: 665 successors: %bb.5.while.body6 666 667 ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp 668 CALL @g, csr, implicit-def dead $rca, implicit $sp, implicit-def $sp, implicit-def $rv 669 ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp 670 671 bb.5.while.body6: 672 successors: %bb.5.while.body6 673 674 BT %bb.5.while.body6 675 676 bb.6.if.end7: 677 RET implicit $rca 678 679... 680