xref: /llvm-project/llvm/test/CodeGen/Hexagon/vect-downscale.ll (revision 2208c97c1bec2512d4e47b6223db6d95a7037956) 
1; RUN: llc -mtriple=hexagon < %s | FileCheck %s
2
3; Make sure we generate a hardware loop and pipeline the inner loop using
4; 4 packets, which is equivalent to the hand-coded version.
5
6; CHECK: loop0(.LBB0_[[LOOP:.]],
7; CHECK: .LBB0_[[LOOP]]:
8; CHECK: {
9; CHECK: }
10; CHECK: {
11; CHECK: }
12; CHECK: {
13; CHECK: }
14; CHECK: {
15; CHECK: }
16; CHECK: {
17; CHECK-NOT: }
18; CHECK: }{{[ \t]*}}:endloop0
19
20define void @f0(ptr noalias %a0, i32 %a1, i32 %a2, i32 %a3, ptr noalias nocapture %a4, i32 %a5, i32 %a6) #0 {
21b0:
22  %v0 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 8388736)
23  %v1 = zext i32 %a3 to i64
24  %v2 = shl nuw i64 %v1, 32
25  %v3 = zext i32 %a1 to i64
26  %v4 = shl nuw nsw i64 %v3, 16
27  %v5 = or i64 %v4, %v2
28  %v6 = or i64 %v5, 281474976710658
29  tail call void asm sideeffect "    l2fetch($0, $1)\0A", "r,r"(ptr %a0, i64 %v6) #2, !srcloc !0
30  %v7 = tail call i32 @llvm.hexagon.S2.ct0(i32 %a6)
31  %v8 = add i32 %v7, 1
32  %v9 = lshr i32 %a1, %v8
33  %v10 = mul i32 %a6, 2
34  %v11 = mul i32 %v10, %v9
35  %v12 = sub i32 %a1, %v11
36  %v13 = lshr i32 %v12, 1
37  %v14 = tail call <64 x i1> @llvm.hexagon.V6.pred.scalar2(i32 %v13)
38  %v15 = icmp eq i32 %a2, 0
39  br i1 %v15, label %b11, label %b1
40
41b1:                                               ; preds = %b0
42  %v16 = mul i32 %a3, 2
43  %v17 = icmp eq i32 %v9, 0
44  %v18 = icmp eq i32 %v11, %a1
45  %v19 = icmp ugt i32 %v12, %a6
46  %v20 = mul i32 %v9, 64
47  %v21 = getelementptr i8, ptr %a4, i32 %v20
48  %v22 = mul i32 %v9, 128
49  %v23 = add i32 %v22, %a3
50  %v24 = getelementptr i8, ptr %a0, i32 %v23
51  %v25 = getelementptr i8, ptr %a0, i32 %v22
52  br label %b2
53
54b2:                                               ; preds = %b10, %b1
55  %v26 = phi ptr [ %v25, %b1 ], [ %v90, %b10 ]
56  %v27 = phi ptr [ %v24, %b1 ], [ %v89, %b10 ]
57  %v28 = phi ptr [ %v21, %b1 ], [ %v88, %b10 ]
58  %v29 = phi <16 x i32> [ undef, %b1 ], [ %v85, %b10 ]
59  %v30 = phi <16 x i32> [ undef, %b1 ], [ %v84, %b10 ]
60  %v31 = phi ptr [ %a0, %b1 ], [ %v86, %b10 ]
61  %v32 = phi ptr [ %a4, %b1 ], [ %v87, %b10 ]
62  %v33 = phi i32 [ 0, %b1 ], [ %v37, %b10 ]
63  %v37 = add nsw i32 %v33, 2
64  %v38 = icmp ult i32 %v37, %a2
65  br i1 %v38, label %b3, label %b4
66
67b3:                                               ; preds = %b2
68  %v39 = getelementptr inbounds i8, ptr %v31, i32 %v16
69  tail call void asm sideeffect "    l2fetch($0, $1)\0A", "r,r"(ptr %v39, i64 %v6) #2, !srcloc !1
70  br label %b4
71
72b4:                                               ; preds = %b3, %b2
73  %v42 = getelementptr inbounds i8, ptr %v31, i32 %a3
74  br i1 %v17, label %b6, label %b5
75
76b5:                                               ; preds = %b5, %b4
77  %v44 = phi ptr [ %v54, %b5 ], [ %v42, %b4 ]
78  %v45 = phi ptr [ %v52, %b5 ], [ %v31, %b4 ]
79  %v46 = phi ptr [ %v61, %b5 ], [ %v32, %b4 ]
80  %v47 = phi i32 [ %v62, %b5 ], [ 0, %b4 ]
81  %v48 = getelementptr inbounds <16 x i32>, ptr %v45, i32 1
82  %v49 = load <16 x i32>, ptr %v45, align 64, !tbaa !2
83  %v50 = getelementptr inbounds <16 x i32>, ptr %v44, i32 1
84  %v51 = load <16 x i32>, ptr %v44, align 64, !tbaa !2
85  %v52 = getelementptr inbounds <16 x i32>, ptr %v45, i32 2
86  %v53 = load <16 x i32>, ptr %v48, align 64, !tbaa !2
87  %v54 = getelementptr inbounds <16 x i32>, ptr %v44, i32 2
88  %v55 = load <16 x i32>, ptr %v50, align 64, !tbaa !2
89  %v56 = tail call <16 x i32> @llvm.hexagon.V6.vdmpybus.acc(<16 x i32> %v0, <16 x i32> %v49, i32 1077952576)
90  %v57 = tail call <16 x i32> @llvm.hexagon.V6.vdmpybus.acc(<16 x i32> %v0, <16 x i32> %v53, i32 1077952576)
91  %v58 = tail call <16 x i32> @llvm.hexagon.V6.vdmpybus.acc(<16 x i32> %v56, <16 x i32> %v51, i32 1077952576)
92  %v59 = tail call <16 x i32> @llvm.hexagon.V6.vdmpybus.acc(<16 x i32> %v57, <16 x i32> %v55, i32 1077952576)
93  %v60 = tail call <16 x i32> @llvm.hexagon.V6.vpackob(<16 x i32> %v59, <16 x i32> %v58)
94  %v61 = getelementptr inbounds <16 x i32>, ptr %v46, i32 1
95  store <16 x i32> %v60, ptr %v46, align 64, !tbaa !2
96  %v62 = add nsw i32 %v47, 1
97  %v63 = icmp eq i32 %v62, %v9
98  br i1 %v63, label %b6, label %b5
99
100b6:                                               ; preds = %b5, %b4
101  %v64 = phi <16 x i32> [ %v29, %b4 ], [ %v55, %b5 ]
102  %v65 = phi <16 x i32> [ %v30, %b4 ], [ %v53, %b5 ]
103  %v66 = phi ptr [ %v42, %b4 ], [ %v27, %b5 ]
104  %v67 = phi ptr [ %v31, %b4 ], [ %v26, %b5 ]
105  %v68 = phi ptr [ %v32, %b4 ], [ %v28, %b5 ]
106  br i1 %v18, label %b10, label %b7
107
108b7:                                               ; preds = %b6
109  %v69 = load <16 x i32>, ptr %v67, align 64, !tbaa !2
110  %v70 = load <16 x i32>, ptr %v66, align 64, !tbaa !2
111  br i1 %v19, label %b8, label %b9
112
113b8:                                               ; preds = %b7
114  %v71 = getelementptr inbounds <16 x i32>, ptr %v66, i32 1
115  %v72 = getelementptr inbounds <16 x i32>, ptr %v67, i32 1
116  %v73 = load <16 x i32>, ptr %v72, align 64, !tbaa !2
117  %v74 = load <16 x i32>, ptr %v71, align 64, !tbaa !2
118  br label %b9
119
120b9:                                               ; preds = %b8, %b7
121  %v75 = phi <16 x i32> [ %v73, %b8 ], [ %v65, %b7 ]
122  %v76 = phi <16 x i32> [ %v74, %b8 ], [ %v64, %b7 ]
123  %v77 = tail call <16 x i32> @llvm.hexagon.V6.vdmpybus.acc(<16 x i32> %v0, <16 x i32> %v69, i32 1077952576)
124  %v78 = tail call <16 x i32> @llvm.hexagon.V6.vdmpybus.acc(<16 x i32> %v0, <16 x i32> %v75, i32 1077952576)
125  %v79 = tail call <16 x i32> @llvm.hexagon.V6.vdmpybus.acc(<16 x i32> %v77, <16 x i32> %v70, i32 1077952576)
126  %v80 = tail call <16 x i32> @llvm.hexagon.V6.vdmpybus.acc(<16 x i32> %v78, <16 x i32> %v76, i32 1077952576)
127  %v81 = tail call <16 x i32> @llvm.hexagon.V6.vpackob(<16 x i32> %v80, <16 x i32> %v79)
128  %v82 = load <16 x i32>, ptr %v68, align 64, !tbaa !2
129  %v83 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<64 x i1> %v14, <16 x i32> %v81, <16 x i32> %v82)
130  store <16 x i32> %v83, ptr %v68, align 64, !tbaa !2
131  br label %b10
132
133b10:                                              ; preds = %b9, %b6
134  %v84 = phi <16 x i32> [ %v75, %b9 ], [ %v65, %b6 ]
135  %v85 = phi <16 x i32> [ %v76, %b9 ], [ %v64, %b6 ]
136  %v86 = getelementptr inbounds i8, ptr %v31, i32 %v16
137  %v87 = getelementptr inbounds i8, ptr %v32, i32 %a5
138  %v88 = getelementptr i8, ptr %v28, i32 %a5
139  %v89 = getelementptr i8, ptr %v27, i32 %v16
140  %v90 = getelementptr i8, ptr %v26, i32 %v16
141  br i1 %v38, label %b2, label %b11
142
143b11:                                              ; preds = %b10, %b0
144  ret void
145}
146
147; Function Attrs: nounwind readnone
148declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1
149
150; Function Attrs: nounwind readnone
151declare i32 @llvm.hexagon.S2.ct0(i32) #1
152
153; Function Attrs: nounwind readnone
154declare <64 x i1> @llvm.hexagon.V6.pred.scalar2(i32) #1
155
156; Function Attrs: nounwind readnone
157declare <16 x i32> @llvm.hexagon.V6.vdmpybus.acc(<16 x i32>, <16 x i32>, i32) #1
158
159; Function Attrs: nounwind readnone
160declare <16 x i32> @llvm.hexagon.V6.vpackob(<16 x i32>, <16 x i32>) #1
161
162; Function Attrs: nounwind readnone
163declare <16 x i32> @llvm.hexagon.V6.vmux(<64 x i1>, <16 x i32>, <16 x i32>) #1
164
165attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
166attributes #1 = { nounwind readnone }
167attributes #2 = { nounwind }
168
169!0 = !{i32 -2146401371}
170!1 = !{i32 -2146401153}
171!2 = !{!3, !3, i64 0}
172!3 = !{!"omnipotent char", !4, i64 0}
173!4 = !{!"Simple C/C++ TBAA"}
174