1; RUN: llc -mtriple=hexagon < %s 2; REQUIRES: asserts 3; Check that llc does not crash. 4 5@g0 = private unnamed_addr constant [7 x i8] c"%d\09\09%d\00", align 1 6@g1 = common global <4 x i32> zeroinitializer, align 16 7 8declare i32 @f0(...) 9 10; Function Attrs: nounwind 11define i32 @f1() #0 { 12b0: 13 %v0 = alloca i32, align 4 14 %v1 = alloca i32, align 4 15 %v2 = alloca [0 x <4 x i32>], align 16 16 store i32 0, ptr %v0 17 store i32 0, ptr %v1, align 4 18 call void @llvm.memset.p0.i32(ptr align 16 %v2, i8 0, i32 0, i1 false) 19 %v4 = load i32, ptr %v1, align 4 20 %v5 = add nsw i32 %v4, 1 21 store i32 %v5, ptr %v1, align 4 22 %v6 = load <4 x i32>, ptr @g1, align 16 23 %v7 = call i32 @f0(ptr @g0, i32 %v5, <4 x i32> %v6) 24 ret i32 0 25} 26 27; Function Attrs: argmemonly nounwind 28declare void @llvm.memset.p0.i32(ptr nocapture writeonly, i8, i32, i1) #1 29 30attributes #0 = { nounwind "target-cpu"="hexagonv60" } 31attributes #1 = { argmemonly nounwind } 32