1; RUN: llc -mtriple=hexagon -O2 -enable-pipeliner=false < %s | FileCheck %s 2; RUN: llc -mtriple=hexagon -O2 -debug-only=pipeliner < %s -o - 2>&1 | FileCheck %s --check-prefix=CHECK-SWP 3; REQUIRES: asserts 4 5; CHECK: { 6; CHECK-DAG: v{{[0-9]*}} = vmem(r{{[0-9]*}}++#1) 7; CHECK-DAG: vmem(r{{[0-9]*}}++#1) = v{{[0-9]*}}.new 8; CHECK: }{{[ \t]*}}:endloop0 9 10; CHECK-SWP: Schedule Found? 1 11; CHECK-SWP: { 12; CHECK-DAG-SWP: v{{[0-9]*}}.cur = vmem(r{{[0-9]*}}++#1) 13; CHECK-DAG-SWP: vmem(r{{[0-9]*}}++#1) = v{{[0-9]*}}.new 14; CHECK-SWP: }{{[ \t]*}}:endloop0 15 16target triple = "hexagon" 17 18; Function Attrs: nounwind 19define void @f0(ptr nocapture readonly %a0, i32 %a1, i32 %a2, ptr nocapture %a3) #0 { 20b0: 21 %v0 = mul i32 %a2, -2 22 %v1 = add i32 %v0, 64 23 %v2 = tail call <16 x i32> @llvm.hexagon.V6.vsubw(<16 x i32> undef, <16 x i32> undef) 24 %v4 = sdiv i32 %a1, 32 25 %v5 = icmp sgt i32 %a1, 31 26 br i1 %v5, label %b1, label %b4 27 28b1: ; preds = %b0 29 %v7 = icmp sgt i32 %a1, 63 30 %v8 = mul i32 %v4, 32 31 %v9 = select i1 %v7, i32 %v8, i32 32 32 %v10 = getelementptr i16, ptr %a3, i32 %v9 33 br label %b2 34 35b2: ; preds = %b2, %b1 36 %v11 = phi i32 [ 0, %b1 ], [ %v19, %b2 ] 37 %v12 = phi <16 x i32> [ %v2, %b1 ], [ %v16, %b2 ] 38 %v13 = phi ptr [ %a3, %b1 ], [ %v18, %b2 ] 39 %v14 = phi ptr [ %a0, %b1 ], [ %v15, %b2 ] 40 %v15 = getelementptr inbounds <16 x i32>, ptr %v14, i32 1 41 %v16 = load <16 x i32>, ptr %v14, align 64, !tbaa !0 42 %v17 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v16, <16 x i32> %v12, i32 %v1) 43 %v18 = getelementptr inbounds <16 x i32>, ptr %v13, i32 1 44 store <16 x i32> %v17, ptr %v13, align 64, !tbaa !0 45 %v19 = add nsw i32 %v11, 1 46 %v20 = icmp slt i32 %v19, %v4 47 br i1 %v20, label %b2, label %b3 48 49b3: ; preds = %b2 50 br label %b4 51 52b4: ; preds = %b3, %b0 53 %v22 = phi <16 x i32> [ %v16, %b3 ], [ %v2, %b0 ] 54 %v23 = phi ptr [ %v10, %b3 ], [ %a3, %b0 ] 55 %v24 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v2, <16 x i32> %v22, i32 %v1) 56 store <16 x i32> %v24, ptr %v23, align 64, !tbaa !0 57 ret void 58} 59 60; Function Attrs: nounwind readnone 61declare <16 x i32> @llvm.hexagon.V6.vsubw(<16 x i32>, <16 x i32>) #1 62 63; Function Attrs: nounwind readnone 64declare <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32>, <16 x i32>, i32) #1 65 66attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } 67attributes #1 = { nounwind readnone } 68 69!0 = !{!1, !1, i64 0} 70!1 = !{!"omnipotent char", !2, i64 0} 71!2 = !{!"Simple C/C++ TBAA"} 72