1; RUN: llc -mtriple=hexagon -O0 < %s | FileCheck %s 2; CHECK: allocframe(r29,#{{[1-9][0-9]*}}):raw 3; CHECK: r29 = and(r29,#-64) 4 5target triple = "hexagon" 6 7; Function Attrs: nounwind 8define i32 @f0() #0 { 9b0: 10 %v0 = alloca <16 x i32>, align 64 11 call void @llvm.lifetime.start.p0(i64 64, ptr %v0) #3 12 %v2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1) 13 %v3 = tail call <16 x i32> @llvm.hexagon.V6.vsubh.rt(<16 x i32> %v2, i32 -1) 14 store <16 x i32> %v3, ptr %v0, align 64, !tbaa !0 15 call void @f1(i32 64, ptr %v0) #3 16 call void @llvm.lifetime.end.p0(i64 64, ptr %v0) #3 17 ret i32 0 18} 19 20; Function Attrs: nounwind readnone 21declare <16 x i32> @llvm.hexagon.V6.vsubh.rt(<16 x i32>, i32) #1 22 23; Function Attrs: nounwind readnone 24declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1 25 26declare void @f1(i32, ptr) #0 27 28; Function Attrs: argmemonly nounwind 29declare void @llvm.lifetime.start.p0(i64, ptr nocapture) #2 30 31; Function Attrs: argmemonly nounwind 32declare void @llvm.lifetime.end.p0(i64, ptr nocapture) #2 33 34attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } 35attributes #1 = { nounwind readnone } 36attributes #2 = { argmemonly nounwind } 37attributes #3 = { nounwind } 38 39!0 = !{!1, !1, i64 0} 40!1 = !{!"omnipotent char", !2, i64 0} 41!2 = !{!"Simple C/C++ TBAA"} 42