xref: /llvm-project/llvm/test/CodeGen/Hexagon/union-1.ll (revision 2208c97c1bec2512d4e47b6223db6d95a7037956)
1; RUN: llc -mtriple=hexagon < %s | FileCheck %s
2; CHECK: f0
3; CHECK-NOT: combine(#0
4; CHECK: jump f1
5
6define void @f0(ptr nocapture %a0) #0 {
7b0:
8  %v0 = load i32, ptr %a0, align 4
9  %v1 = zext i32 %v0 to i64
10  %v2 = getelementptr inbounds i32, ptr %a0, i32 1
11  %v3 = load i32, ptr %v2, align 4
12  %v4 = zext i32 %v3 to i64
13  %v5 = shl nuw i64 %v4, 32
14  %v6 = or i64 %v5, %v1
15  tail call void @f1(i64 %v6) #0
16  ret void
17}
18
19declare void @f1(i64) #0
20
21attributes #0 = { nounwind "target-cpu"="hexagonv5" }
22