1; RUN: llc -mtriple=hexagon -enable-pipeliner-opt-size -hexagon-initial-cfg-cleanup=0 < %s -pipeliner-experimental-cg=true | FileCheck %s 2 3; Test that we generate the correct names for the phis in the kernel for the 4; incoming values. In this case, the loop contains a phi and has another phi 5; as its loop definition, and the two phis are scheduled in different stages. 6; 7; vreg5 = phi(x, vreg4) is scheduled in stage 1, cycle 0 8; vreg4 = phi(y, z) is scheduled in stage 0, cycle 0 9 10; CHECK-DAG: :[[REG0:[0-9]+]]{{.*}} = {{.*}},#17 11; CHECK-DAG: loop0(.LBB0_[[LOOP:.]], 12; CHECK: .LBB0_[[LOOP]]: 13; CHECK: r{{[0-9]+}} = sxth(r[[REG0]]) 14; CHECK: endloop0 15 16; Function Attrs: nounwind optsize 17define void @f0() #0 { 18b0: 19 %v0 = getelementptr [8 x i16], ptr undef, i32 0, i32 7 20 br label %b2 21 22b1: ; preds = %b2 23 unreachable 24 25b2: ; preds = %b2, %b0 26 %v2 = phi i32 [ 7, %b0 ], [ %v11, %b2 ] 27 %v3 = phi i16 [ 17, %b0 ], [ %v7, %b2 ] 28 %v4 = phi i16 [ 18, %b0 ], [ %v3, %b2 ] 29 %v5 = sext i16 %v4 to i32 30 %v6 = getelementptr i16, ptr null, i32 -2 31 %v7 = load i16, ptr %v6, align 2 32 %v8 = sext i16 %v7 to i32 33 %v9 = tail call i32 @llvm.hexagon.A2.subsat(i32 %v5, i32 %v8) 34 %v10 = trunc i32 %v9 to i16 35 store i16 %v10, ptr null, align 2 36 %v11 = add nsw i32 %v2, -1 37 %v12 = icmp sgt i32 %v11, 1 38 br i1 %v12, label %b2, label %b1 39} 40 41; Function Attrs: nounwind readnone 42declare i32 @llvm.hexagon.A2.subsat(i32, i32) #1 43 44attributes #0 = { nounwind optsize "target-cpu"="hexagonv60" } 45attributes #1 = { nounwind readnone } 46