xref: /llvm-project/llvm/test/CodeGen/Hexagon/simplify64bitops_7223.ll (revision 2208c97c1bec2512d4e47b6223db6d95a7037956)
1; RUN: llc -mtriple=hexagon -enable-pipeliner=false < %s | FileCheck %s
2; RUN: llc -mtriple=hexagon -enable-pipeliner < %s
3; REQUIRES: asserts
4; CHECK-NOT: and(
5; CHECK-NOT: or(
6; CHECK-NOT: combine(0
7; CHECK: add
8; CHECK: add(
9; CHECK-NEXT: memuh(
10; CHECK-NEXT: endloop
11
12%s.22 = type { i64 }
13
14@g0 = common global i32 0, align 4
15
16; Function Attrs: nounwind
17define i64 @f0(ptr nocapture %a0, i32 %a1) #0 {
18b0:
19  %v1 = load i16, ptr %a0, align 2, !tbaa !0
20  %v2 = zext i16 %v1 to i64
21  %v3 = icmp sgt i32 %a1, 0
22  br i1 %v3, label %b1, label %b4
23
24b1:                                               ; preds = %b0
25  br label %b2
26
27b2:                                               ; preds = %b2, %b1
28  %v4 = phi ptr [ %v8, %b2 ], [ %a0, %b1 ]
29  %v5 = phi i32 [ %v10, %b2 ], [ undef, %b1 ]
30  %v6 = phi i32 [ %v15, %b2 ], [ 0, %b1 ]
31  %v7 = phi i64 [ %v14, %b2 ], [ %v2, %b1 ]
32  %v8 = getelementptr inbounds i16, ptr %v4, i32 1
33  %v9 = trunc i64 %v7 to i32
34  %v10 = add i32 %v5, %v9
35  %v11 = load i16, ptr %v8, align 2, !tbaa !0
36  %v12 = zext i16 %v11 to i64
37  %v13 = and i64 %v7, -4294967296
38  %v14 = or i64 %v12, %v13
39  %v15 = add nsw i32 %v6, 1
40  %v16 = icmp eq i32 %v15, %a1
41  br i1 %v16, label %b3, label %b2
42
43b3:                                               ; preds = %b2
44  br label %b4
45
46b4:                                               ; preds = %b3, %b0
47  %v17 = phi i32 [ undef, %b0 ], [ %v10, %b3 ]
48  %v18 = phi i64 [ %v2, %b0 ], [ %v14, %b3 ]
49  store volatile i32 %v17, ptr @g0, align 4, !tbaa !4
50  ret i64 %v18
51}
52
53attributes #0 = { nounwind }
54
55!0 = !{!1, !1, i64 0}
56!1 = !{!"short", !2}
57!2 = !{!"omnipotent char", !3}
58!3 = !{!"Simple C/C++ TBAA"}
59!4 = !{!5, !5, i64 0}
60!5 = !{!"long", !2}
61