xref: /llvm-project/llvm/test/CodeGen/Hexagon/sdiv-minsigned.ll (revision 2208c97c1bec2512d4e47b6223db6d95a7037956)
1; RUN: llc -mtriple=hexagon < %s | FileCheck %s
2; REQUIRES: asserts
3
4; This checks for a bug in the DAG combiner where a SETCC was created with
5; an illegal return type. Make sure it compiles successfully.
6; CHECK: r0 = cmp.eq(r0,##-2147483648)
7
8define i32 @f0(i32 %a0) #0 {
9entry:
10   %v0 = sdiv i32 %a0, -2147483648
11   ret i32 %v0
12}
13
14attributes #0 = { noinline nounwind "target-cpu"="hexagonv60" }
15